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1. 发明授权

US08125816B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08125816B2
公开(公告)日：2012-02-28
申请号：US12488450
申请日：2009-06-19
申请人： Ryousuke Takizawa , Shinichiro Shiratake
发明人： Ryousuke Takizawa , Shinichiro Shiratake
IPC分类号： G11C11/22
CPC分类号： G11C7/12 , G11C7/22 , G11C11/22 , G11C11/4074 , G11C11/4076 , G11C11/4094 , G11C29/08
摘要： According to the present invention, a semiconductor storage device includes: a first memory cell array including: a first bit line; a first plate line; a first memory cell; a first sense amplifier; a first reference power line configured to supply first reference voltage; a first switching module configured to control a connection between the first reference power line and the first bit line; a second memory cell array including: a second bit line; a second plate line; a second memory cell; a second sense amplifier; a second reference power line configured to supply second reference voltage; a second switching module configured to control a connection between the second reference power line and the second bit line; a control module configured to generate the control signal so as to control a time difference between the first memory cell array and the second memory cell array in precharge operation.
摘要翻译：根据本发明，半导体存储装置包括：第一存储单元阵列，包括：第一位线; 第一板线第一存储单元; 第一感测放大器; 第一参考电源线，被配置为提供第一参考电压; 第一切换模块，被配置为控制所述第一参考电力线和所述第一位线之间的连接; 第二存储单元阵列，包括：第二位线; 第二板线; 第二存储单元; 第二感测放大器; 配置为提供第二参考电压的第二参考电源线; 第二切换模块，被配置为控制所述第二参考电力线和所述第二位线之间的连接; 控制模块，被配置为产生控制信号，以便在预充电操作中控制第一存储单元阵列和第二存储单元阵列之间的时间差。

2. 发明申请

US20090323390A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20090323390A1
公开(公告)日：2009-12-31
申请号：US12422083
申请日：2009-04-10
申请人： Ryousuke Takizawa , Shinichiro Shiratake
发明人： Ryousuke Takizawa , Shinichiro Shiratake
IPC分类号： G11C11/22 , G11C11/24 , G11C8/08 , G11C7/02
CPC分类号： G11C11/22 , G11C8/08
摘要： A memory includes a cell block including ferroelectric capacitors and cell transistors, the cell block being configured by unit cells formed by the ferroelectric capacitor and the cell transistor; a dummy block configured by having one end of dummy strings connected in common, the dummy string being formed by connecting in series dummy transistors; dummy word lines connected to gates of the dummy transistors; a dummy block selection transistor connected between the dummy block and a bit line; wherein in a data read operation, a dummy-word-line driver sets the dummy transistors to a conductive state, the number of the dummy transistors in the conductive state depends on the number of the cell transistors present between the unit cell to be read and the bit line, and the dummy transistors in a conductive state are conductive to the bit line.
摘要翻译：存储器包括：包括铁电电容器和单元晶体管的单元块，所述单元块由所述铁电电容器和所述单元晶体管形成的单位单元构成; 通过将虚设串的一端共同连接而构成的虚拟块，通过连接虚拟晶体管形成虚设串; 连接到虚拟晶体管的栅极的虚拟字线; 连接在虚拟块和位线之间的虚拟块选择晶体管; 其中在数据读取操作中，虚拟字线驱动器将虚拟晶体管设置为导通状态，导通状态中的虚设晶体管的数量取决于存在于要读取的单元单元之间的单元晶体管的数量和位线和导通状态的虚拟晶体管对位线是导通的。

3. 发明申请

US20090256542A1 POWER SUPPLY CIRCUIT 失效
标题翻译：电源电路
公开(公告)号：US20090256542A1
公开(公告)日：2009-10-15
申请号：US12404438
申请日：2009-03-16
申请人： Hidehiro SHIGA , Shinichiro Shiratake , Daisaburo Takashima
发明人： Hidehiro SHIGA , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G05F1/10
CPC分类号： G05F1/56
摘要： A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.
摘要翻译：电源电路具有恒压电路，第一MOS晶体管，第二MOS晶体管，第三MOS晶体管，第一分压电路，输出通过将输出端子的电压除以第一分压而得到的第一分压以及馈送有参考电压的第一差分放大器电路和第一分压，并且具有连接到第二MOS晶体管的栅极的输出。当第一分压高于参考电压时，第一差分放大器电路输出信号以接通第二MOS晶体管，并且当第一分压电压较低时，第一差分放大器电路输出关闭第二MOS晶体管的信号比参考电压。

4. 发明授权

US07397687B2 Ferroelectric memory device having ferroelectric capacitor 失效
标题翻译：具有铁电电容器的铁电存储器件
公开(公告)号：US07397687B2
公开(公告)日：2008-07-08
申请号：US11447940
申请日：2006-06-07
申请人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
发明人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a cell block, a bit line, and a plate line. The cell block includes a ferroelectric capacitor and a transistor switch. The bit line applies a voltage to one electrode of the ferroelectric capacitor. The plate line applies a voltage to the other electrode of the ferroelectric capacitor. In a read operation of data, a first voltage is applied to the plate line. In a write operation of data, a second voltage different from the first voltage is applied to the plate line, and a voltage which is higher or lower than the second voltage is applied to the bit line.
摘要翻译：铁电存储器件包括电池块，位线和板线。电池块包括铁电电容器和晶体管开关。位线向铁电电容器的一个电极施加电压。板线向铁电电容器的另一个电极施加电压。在数据的读取操作中，向板线施加第一电压。在数据的写入操作中，不同于第一电压的第二电压被施加到板线，并且高于或低于第二电压的电压被施加到位线。

5. 发明授权

US07236035B2 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US07236035B2
公开(公告)日：2007-06-26
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

6. 发明授权

US07218546B2 Integrated circuit device provided with series-connected TC parallel unit ferroelectric memory and method for testing the same 有权
标题翻译：具有串联连接的TC并联单元铁电存储器的集成电路器件及其测试方法
公开(公告)号：US07218546B2
公开(公告)日：2007-05-15
申请号：US11109769
申请日：2005-04-20
申请人： Tadashi Miyakawa , Daisaburo Takashima , Shinichiro Shiratake
发明人： Tadashi Miyakawa , Daisaburo Takashima , Shinichiro Shiratake
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： G11C29/50 , G11C8/08 , G11C11/22 , G11C2029/1202
摘要： An integrated circuit device comprises a memory cell block, a word line selecting circuit and a driving circuit. The memory cell block comprises memory cells connected in series. The memory cell comprises a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor connected to terminals of the cell transistor. The word line selecting circuit successively selects the word lines connected to the cell transistors in the memory cells in the memory cell block in response to address signals successively input from an outside of the device, during an active cycle. The driving circuit applies a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, during a time period for which the word lines connected to the cell transistors are successively selected by the word line selecting circuit.
摘要翻译：集成电路装置包括存储单元块，字线选择电路和驱动电路。存储单元块包括串联连接的存储器单元。存储单元包括单元晶体管，其包括连接到字线的栅极和连接到单元晶体管的端子的铁电电容器。在活动周期期间，字线选择电路响应于从设备的外部连续输入的地址信号，连续地选择连接到存储单元块中的单元晶体管的字线。在通过字线选择连续选择连接到单元晶体管的字线的时间段期间，驱动电路在存储单元块的存储单元中由单元晶体管提供的电流路径的两端之间施加给定电压电路。

7. 发明申请

US20060198198A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20060198198A1
公开(公告)日：2006-09-07
申请号：US11342617
申请日：2006-01-31
申请人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
发明人： Tetsuya Fujita , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara , Shinichiro Shiratake
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C5/147
摘要： According to the present invention, there is provided a semiconductor integrated circuit comprising: a power controller which outputs a voltage select signal for selecting one of at least two types of voltages; a power supply voltage controller which generates and outputs a power supply voltage at an arbitrary voltage change rate on the basis of the voltage select signal; and a circuit portion which receives the power supply voltage and performs processing, wherein said circuit portion keeps operating while said power supply voltage controller is outputting the power supply voltage generated at the arbitrary voltage change rate.
摘要翻译：根据本发明，提供了一种半导体集成电路，包括：功率控制器，其输出用于选择至少两种类型的电压中的一种的电压选择信号; 电源电压控制器，其基于所述电压选择信号生成并输出任意电压变化率的电源电压; 以及电路部分，其接收电源电压并执行处理，其中所述电路部分在所述电源电压控制器输出以任意电压变化率产生的电源电压的情况下保持操作。

8. 发明授权

US07016216B2 Ferroelectric memory device having ferroelectric capacitor and method of reading out data therefrom 失效
标题翻译：具有铁电电容器的铁电存储器件和从其读出数据的方法
公开(公告)号：US07016216B2
公开(公告)日：2006-03-21
申请号：US10680394
申请日：2003-10-08
申请人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
发明人： Kohei Oikawa , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes memory cells, a memory cell block, a sense amplifier, a precharge circuit, a bit line drive circuit, and a plate line drive circuit. Each of the memory cells has a cell transistor and a ferroelectric capacitor in between a source and drain of the cell transistor. The memory cell block includes the memory cells that are series connected between a bit line via a block select transistor and a plate line. The sense amplifier amplifies data read out from the memory cell, and generates one of a first potential and a second potential higher than the first potential in accordance with the read-out data. The precharge circuit precharges the bit line at a third potential that is higher than the first potential and lower than the second potential. The bit line drive circuit sets the bit line at a fourth potential.
摘要翻译：铁电存储器件包括存储单元，存储单元块，读出放大器，预充电电路，位线驱动电路和板线驱动电路。每个存储单元在单元晶体管的源极和漏极之间具有单元晶体管和铁电电容器。存储单元块包括串联连接在经由块选择晶体管的位线和板线之间的存储单元。读出放大器放大从存储单元读出的数据，根据读出的数据产生高于第一电位的第一电位和第二电位中的一个。预充电电路在比第一电位高且低于第二电位的第三电位预充电位线。位线驱动电路将位线设置为第四个电位。

9. 发明授权

US06990007B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06990007B2
公开(公告)日：2006-01-24
申请号：US10893949
申请日：2004-07-20
申请人： Shinichiro Shiratake
发明人： Shinichiro Shiratake
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor memory device includes a first cell group having serial-connected memory cells. The memory cell includes a ferroelectric capacitor and a transistor which are connected in parallel. A first bit line is selectively electrically connected to one end of the first cell group. A second bit line is selectively electrically connected to the other end of the first cell group. A first power supply connection circuit selectively electrically connects a power supply line having a first potential to the second bit line. A sense amplifier has a first terminal electrically connected to the first bit line, generates one of first and second potentials onto the first terminal according to data stored in the memory cell and generates the other one of the first and second potentials onto a second terminal thereof. A first bit line connection circuit selectively electrically connects the second terminal to the second bit line.
摘要翻译：半导体存储器件包括具有串联存储单元的第一单元组。存储单元包括并联连接的铁电电容器和晶体管。第一位线选择性地电连接到第一单元组的一端。第二位线选择性地电连接到第一单元组的另一端。第一电源连接电路将具有第一电位的电源线选择性地电连接到第二位线。读出放大器具有电连接到第一位线的第一端子，根据存储在存储单元中的数据，将第一和第二电位中的一个产生到第一端上，并将第一和第二电位中的另一个电位产生到第二端。第一位线连接电路选择性地将第二端子电连接到第二位线。

10. 发明申请

US20050275450A1 Booster circuit 失效
标题翻译：增压电路
公开(公告)号：US20050275450A1
公开(公告)日：2005-12-15
申请号：US10923717
申请日：2004-08-24
申请人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
发明人： Hidehiro Shiga , Shinichiro Shiratake , Daisaburo Takashima
IPC分类号： H02M3/07 , G05F3/02
CPC分类号： H02M3/073 , H02M2001/0041 , H02M2003/077
摘要： A booster circuit includes a first booster unit having a first output terminal from which a boosted voltage is output. The first output terminal is connected to an external output terminal. A second booster unit has a second output terminal from which a boosted voltage is output. The second output terminal is connected to the external output terminal. A control circuit outputs a first control signal used to control the operation of the first booster unit and a second control signal used to control the operation of the second booster unit. Further, the control circuit controls the first and second control signals so that a transition between the operative state and the non-operative state of the first booster unit and a transition between the operative state and the non-operative state of the second booster unit will be made at different timings according to output voltage of the external output terminal.
摘要翻译：升压电路包括具有输出升压电压的第一输出端的第一升压单元。第一个输出端子连接到一个外部输出端子。第二升压单元具有输出升压电压的第二输出端子。第二个输出端子连接到外部输出端子。控制电路输出用于控制第一升压单元的运行的第一控制信号和用于控制第二升压单元的运行的第二控制信号。此外，控制电路控制第一和第二控制信号，使得第一升压单元的操作状态和非操作状态之间的转变以及第二增压单元的操作状态和非操作状态之间的转变将根据外部输出端子的输出电压在不同的定时进行。

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