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1. 发明授权

US5831901A Method of programming a memory cell to contain multiple values 失效
标题翻译：将存储单元编程为包含多个值的方法
公开(公告)号：US5831901A
公开(公告)日：1998-11-03
申请号：US745596
申请日：1996-11-08
申请人： Yuan Tang , Qimeng Zhou , Hsingya Arthur Wang
发明人： Yuan Tang , Qimeng Zhou , Hsingya Arthur Wang
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C2211/5625
摘要： A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.
摘要翻译：公开了一种在单个闪速存储器单元中编程多个值的方法。通过将对应于特定存储器单元的位线保持为Vd来编程单个闪存单元，同时存储单元的控制栅极Vg上的电压变化。通过改变控制栅极上的电压，多个值被存储在存储单元中。所得到的值是自收敛的，因此，验证电路变得不必要。

2. 发明授权

US5763307A Block select transistor and method of fabrication 失效
标题翻译：块选择晶体管及其制造方法
公开(公告)号：US5763307A
公开(公告)日：1998-06-09
申请号：US745278
申请日：1996-11-08
申请人： Hsingya Arthur Wang , Qimeng Zhou
发明人： Hsingya Arthur Wang , Qimeng Zhou
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11534
摘要： A flash memory device having a reduced area is disclosed. The device uses a polyI layer to act as a select transistor for the memory cells comprising the core array. Also, a ground plate is used to isolate the areas of the memory array where high voltage devices should not be located, thereby allowing peripheral components to be fabricated in the core array area. Also disclosed is a polyII layer used to access two sublines controlling two different sectors of the memory array architecture. By using such a layout, die space savings is attained.
摘要翻译：公开了一种具有减小的面积的闪速存储器件。该器件使用polyI层作为包括核心阵列的存储器单元的选择晶体管。此外，接地板用于隔离存储器阵列中不应该位于高电压器件的区域，从而允许在核心阵列区域中制造外围元件。还公开了用于访问控制存储器阵列架构的两个不同扇区的两个子线的polyII层。通过使用这种布局，可以节省模具空间。

3. 发明授权

US5882985A Reduction of field oxide step height during semiconductor fabrication 失效
标题翻译：在半导体制造期间减小场氧化物步长
公开(公告)号：US5882985A
公开(公告)日：1999-03-16
申请号：US541927
申请日：1995-10-10
申请人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
发明人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： A method for reducing the steep step at the edge of a locally oxidized, field oxide boundary region as a result of using the local oxidation of silicon (LOCOS) method to isolate the active regions of a semiconductor wafer. The reduction is carried out by applying a planarizing layer to the field oxide layer and then etching back the planarizing layer and field oxide layer to a desired thickness.
摘要翻译：作为使用硅的局部氧化（LOCOS）方法的局部氧化的场氧化物边界区域的边缘处的陡峭步骤的方法来隔离半导体晶片的有源区域的方法。通过将平坦化层施加到场氧化物层，然后将平坦化层和场氧化物层回蚀刻到期望的厚度来进行还原。

4. 发明授权

US5920506A Method and apparatus for bulk preprogramming flash memory cells with minimal source and drain currents 失效
标题翻译：用于批量预编程具有最小源极和漏极电流的闪存单元的方法和装置
公开(公告)号：US5920506A
公开(公告)日：1999-07-06
申请号：US938389
申请日：1997-09-26
申请人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
发明人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
IPC分类号： G11C16/10 , G11C16/16 , G11C16/04
CPC分类号： G11C16/107 , G11C16/10 , G11C16/16 , G11C2216/16
摘要： Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.
摘要翻译：提供了设备以便于批量预编程闪速存储器或闪速存储器的子块中的每个单元的处理。在该过程中，要预编程的每个单元的源极和漏极被偏置，使得电流不需要在源极和漏极之间通过电池的沟道区域流动，以在电池的沟道区域和电池的浮动栅极之间传输电荷。在具体实施例中，源极和漏极在没有任何特定偏置电压的情况下保持浮置，并且单元的控制栅极被设置在衬底上方9到12伏之间并保持在大约10毫秒（ms）。在替代实施例中，要预编程的所有单元的源极和漏极被偏置到相同的电位，其是负电压，接地或正电压。

5. 发明授权

US07154141B2 Source side programming 有权
公开(公告)号：US07154141B2
公开(公告)日：2006-12-26
申请号：US09777007
申请日：2001-02-02
申请人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
发明人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/10
摘要： A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.

6. 发明授权

US07250341B2 Flash memory device having poly spacers 失效
标题翻译：具有聚间隔物的闪存器件
公开(公告)号：US07250341B2
公开(公告)日：2007-07-31
申请号：US11100123
申请日：2005-04-05
申请人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
发明人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.
摘要翻译：非易失性存储器件包括具有第一有源区和第二有源区的衬底。第一浮动栅极设置在第一有源区上并具有边缘，第一浮栅由导电材料制成。第一间隔件连接到第一浮栅的边缘并由与第一浮栅相同的导电材料制成。控制门靠近浮动栅极设置。

7. 发明授权

US06777741B2 Non-volatile memory cells with selectively formed floating gate 失效
标题翻译：具有选择性形成的浮动栅极的非易失性存储单元
公开(公告)号：US06777741B2
公开(公告)日：2004-08-17
申请号：US10393603
申请日：2003-03-19
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.
摘要翻译：提供了非易失性存储晶体管，其包括由第一和第二层材料（例如多晶硅）形成的浮置栅极。第二浮栅层选择性地生长或沉积在第一栅极层的顶部上，消除了对第二浮栅层定位的掩模的需要。存储晶体管由隔离区域分隔开。第二浮栅层与隔离区域的一部分重叠以提供高控制栅 - 浮栅耦合比。该过程使更小的存储晶体管。浮栅为隔离重叠，因此浮栅为浮栅间隔，通过第二多晶硅层的选择性沉积或选择性外延生长来控制。

8. 发明授权

US6043123A Triple well flash memory fabrication process 失效
标题翻译：三重闪存制造工艺
公开(公告)号：US6043123A
公开(公告)日：2000-03-28
申请号：US863917
申请日：1997-05-27
申请人： Hsingya Arthur Wang , Jein-Chen Young , Ming-Sang Kwan
发明人： Hsingya Arthur Wang , Jein-Chen Young , Ming-Sang Kwan
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546
摘要： A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.
摘要翻译：描述了在半导体衬底中制造集成电路存储器的过程。在衬底中，通过引入与衬底的导电性相反的掺杂剂形成第一阱。在第一阱内，第二阱由与衬底相匹配的导电类型形成。存储单元被制造在第二阱中并且具有与导电类型衬底相对的源区和漏区。第一和第二孔中的每一个还包括相应导电类型的区域，以使得能够对每个孔进行单独的电连接。

9. 发明授权

US5981364A Method of forming a silicon gate to produce silicon devices with improved performance 失效
标题翻译：形成硅栅极以产生具有改进性能的硅器件的方法
公开(公告)号：US5981364A
公开(公告)日：1999-11-09
申请号：US568195
申请日：1995-12-06
申请人： Mark T. Ramsbey , Hsingya Arthur Wang , Yu Sun
发明人： Mark T. Ramsbey , Hsingya Arthur Wang , Yu Sun
IPC分类号： H01L21/28 , H01L29/49
CPC分类号： H01L21/28035 , H01L29/4925
摘要： Disclosed herein is a method of forming a silicon gate stack onto a silicon substrate for a silicon device. The method of forming the silicon gate stack comprises the steps of growing an oxide layer onto the silicon substrate, depositing a thin layer of silicon to form a thin layer of silicon over the oxide layer, depositing a thick layer of silicon over the thin layer of silicon, and introducing impurities into only the thick layer of silicon to form a silicon gate whereby the silicon gate includes the thin layer of silicon and the thick layer of silicon having the impurities. The impurities being introduced with a concentration, the impurities concentration and the thick layer thickness impeding an encroachment by the oxide layer into the silicon gate during application of a protective screen oxide layer around the silicon gate stack.
摘要翻译：本文公开了一种在硅器件的硅衬底上形成硅栅叠层的方法。形成硅栅极堆叠的方法包括以下步骤：在硅衬底上生长氧化物层，沉积薄层的硅以在氧化物层上形成薄的硅层，在薄层上沉积厚的硅层硅，并且将杂质引入仅硅的厚层中以形成硅栅极，由此硅栅极包括硅的薄层和具有杂质的厚的硅层。引入浓度的杂质，杂质浓度和厚层厚度在施加硅栅堆叠周围的保护性屏蔽氧化物层时阻碍氧化层侵入硅栅中。

10. 发明授权

US5776811A Simplified process for fabricating flash eeprom cells 失效
标题翻译：制造闪光电池的简化过程
公开(公告)号：US5776811A
公开(公告)日：1998-07-07
申请号：US582720
申请日：1996-01-04
申请人： Hsingya Arthur Wang , Jian Chen , Paul J. Steffan
发明人： Hsingya Arthur Wang , Jian Chen , Paul J. Steffan
IPC分类号： H01L21/336 , H01L29/788 , H01L21/8247
CPC分类号： H01L29/66825 , H01L29/7885
摘要： A simplified fabrication procedure for making flash EEPROM memory cells is disclosed. The method comprises performing a double-diffuse (deep) junction implant after the shallow source/drain of the memory cell have been implanted and formed. A high energy double-diffuse implant is used to replace separate, individual implant and diffusion steps which results in a memory cell having, less damage to its substrate.
摘要翻译：公开了一种用于制造快速EEPROM存储单元的简化制造程序。该方法包括在已经注入和形成存储单元的浅源极/漏极之后执行双扩散（深）结注入。高能双漫射植入物被用于代替单独的个体注入和扩散步骤，导致记忆单元对其底物的损伤较小。

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