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1. 发明授权

US07250341B2 Flash memory device having poly spacers 失效
标题翻译：具有聚间隔物的闪存器件
公开(公告)号：US07250341B2
公开(公告)日：2007-07-31
申请号：US11100123
申请日：2005-04-05
申请人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
发明人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.
摘要翻译：非易失性存储器件包括具有第一有源区和第二有源区的衬底。第一浮动栅极设置在第一有源区上并具有边缘，第一浮栅由导电材料制成。第一间隔件连接到第一浮栅的边缘并由与第一浮栅相同的导电材料制成。控制门靠近浮动栅极设置。

2. 发明授权

US06777741B2 Non-volatile memory cells with selectively formed floating gate 失效
标题翻译：具有选择性形成的浮动栅极的非易失性存储单元
公开(公告)号：US06777741B2
公开(公告)日：2004-08-17
申请号：US10393603
申请日：2003-03-19
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.
摘要翻译：提供了非易失性存储晶体管，其包括由第一和第二层材料（例如多晶硅）形成的浮置栅极。第二浮栅层选择性地生长或沉积在第一栅极层的顶部上，消除了对第二浮栅层定位的掩模的需要。存储晶体管由隔离区域分隔开。第二浮栅层与隔离区域的一部分重叠以提供高控制栅 - 浮栅耦合比。该过程使更小的存储晶体管。浮栅为隔离重叠，因此浮栅为浮栅间隔，通过第二多晶硅层的选择性沉积或选择性外延生长来控制。

3. 发明授权

US08288219B2 Method of forming a non-volatile memory cell using off-set spacers 有权
标题翻译：使用偏置间隔物形成非易失性存储单元的方法
公开(公告)号：US08288219B2
公开(公告)日：2012-10-16
申请号：US12052374
申请日：2008-03-20
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A stack of two polysilicon layers is formed over a semiconductor body region. A DDD implant is performed to form a DDD source region in the semiconductor body region along a source side of the polysilicon stack but not along a drain side of the polysilicon stack. Off-set spacers are formed along opposing side-walls of the polysilicon stack. A source/drain implant is performed to form a drain region in the semiconductor body region along the drain side of the polysilicon stack and to form a highly doped region within the DDD source region such that the extent of an overlap between the polysilicon stack and each of the drain region and the highly doped region is inversely dependent on a thickness of the off-set spacers, and a lateral spacing directly under the polysilicon stack between adjacent edges of the DDD source region and the highly doped region is directly dependent on the thickness of the off-set spacers.
摘要翻译：在半导体主体区域上形成一叠两层多晶硅层。执行DDD注入以在半导体主体区域中沿着多晶硅堆叠的源极侧形成DDD源极区域，但不沿着多晶硅叠层的漏极侧。偏移间隔物沿着多晶硅堆叠的相对侧壁形成。进行源极/漏极注入以沿着多晶硅堆叠的漏极侧在半导体主体区域中形成漏极区域，并且在DDD源极区域内形成高度掺杂的区域，使得多晶硅堆叠和每个漏极区域和高掺杂区域的反向取决于偏置间隔物的厚度，并且在DDD源极区域和高度掺杂区域的相邻边缘之间直接在多晶硅堆叠下面的横向间隔直接取决于厚度的偏置间隔物。

4. 发明授权

US07202134B2 Method of forming transistors with ultra-short gate feature 有权
标题翻译：具有超短栅极特性的晶体管形成方法
公开(公告)号：US07202134B2
公开(公告)日：2007-04-10
申请号：US11022005
申请日：2004-12-21
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A gate electrode is formed over but insulated from a semiconductor body region for each of first and second transistors. A DDD implant is carried out to from DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a LDD implant is carried out to from LDD source and drain regions in the body region for the second transistor. After the LDD implant, main spacers are formed adjacent the off-set spacers of at least the second transistor. After forming the main spacers, a source/drain implant is carried out to form a highly doped region within each of the DDD drain and source regions and the LDD drain and source regions.
摘要翻译：对于第一和第二晶体管中的每一个，栅电极形成在半导体本体区域的绝缘上。从DDD源和DDD漏极区域对第一晶体管进行DDD注入。在DDD植入之后，沿着第一和第二晶体管的每一个的栅电极的侧壁形成偏置间隔物。在形成偏置间隔物之后，从第二晶体管的体区中的LDD源极和漏极区域执行LDD注入。在LDD注入之后，主间隔物形成在至少第二晶体管的偏置间隔物附近。在形成主间隔物之后，进行源极/漏极注入以在每个DDD漏极和源极区域以及LDD漏极和源极区域内形成高掺杂区域。

5. 发明申请

US20050186739A1 Flash memory device having poly spacers 失效
公开(公告)号：US20050186739A1
公开(公告)日：2005-08-25
申请号：US11100123
申请日：2005-04-05
申请人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
发明人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.

6. 发明授权

US06746906B2 Transistor with ultra-short gate feature and method of fabricating the same 有权
标题翻译：具有超短栅极特性的晶体管及其制造方法
公开(公告)号：US06746906B2
公开(公告)日：2004-06-08
申请号：US09808097
申请日：2001-03-13
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21265
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： In one embodiment of the present invention, a method of forming semiconductor transistors includes: forming a gate electrode over but insulated from a semiconductor body region; forming off-set spacers along side-walls of the gate electrode; and after forming said off-set spacers, forming a source region and a drain region in the body region so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on a thickness of the off-set spacers. In another embodiment, a method of forming a non-volatile memory cell includes: forming a first polysilicon layer over but insulated from a semiconductor body region; forming a second polysilicon layer over but insulated from the first polysilicon layer; forming an off-set spacer along at least one side-wall of the first and second polysilicon layers; and after forming said off-set spacer, forming at least one of source and drain regions in the body region so that the extent of an overlap between the first polysilicon layer and said one of source and drain regions is dependent on a thickness of the off-set spacer.
摘要翻译：在本发明的一个实施例中，形成半导体晶体管的方法包括：在半导体本体区域上形成绝缘的栅电极; 沿着栅电极的侧壁形成偏置间隔物; 并且在形成所述偏置间隔物之后，在体区域中形成源极区域和漏极区域，使得栅极电极和源极区域和漏极区域中的每一个之间的重叠程度取决于偏移的厚度间隔物在另一个实施例中，形成非易失性存储单元的方法包括：在半导体本体区域之上形成绝缘的第一多晶硅层; 在第一多晶硅层上形成第二多晶硅层，但与第一多晶硅层绝缘; 沿着所述第一和第二多晶硅层的至少一个侧壁形成偏置间隔物; 并且在形成所述偏置间隔物之后，在体区中形成源区和漏区中的至少一个，使得第一多晶硅层与所述源极和漏极区之间的重叠程度取决于关闭的厚度设置间隔。

7. 发明授权

US08946003B2 Method of forming transistors with ultra-short gate feature 有权
标题翻译：具有超短栅极特性的晶体管形成方法
公开(公告)号：US08946003B2
公开(公告)日：2015-02-03
申请号：US11676777
申请日：2007-02-20
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/8232 , H01L21/8234 , H01L27/115 , H01L27/105 , H01L29/423
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.
摘要翻译：如下形成半导体晶体管。栅电极形成在半导体本体区域上而与半导体本体区域绝缘。第一层绝缘材料形成在栅电极和半导体本体区域上。与第一绝缘材料层不同的第二绝缘材料层形成在第一绝缘材料层上。仅蚀刻绝缘材料的第二层，沿着栅电极的侧壁形成间隔物。通过第一绝缘材料层注入杂质以在体区域中形成源极区域和漏极区域。去除在源区和漏区上延伸的第一层绝缘材料的那些部分的大部分。

8. 发明授权

US06911370B2 Flash memory device having poly spacers 失效
标题翻译：具有聚间隔物的闪存器件
公开(公告)号：US06911370B2
公开(公告)日：2005-06-28
申请号：US10431172
申请日：2003-05-06
申请人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
发明人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/331 , H01L21/8222
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.
摘要翻译：非易失性存储器件包括具有第一有源区和第二有源区的衬底。第一浮动栅极设置在第一有源区上并具有边缘，第一浮栅由导电材料制成。第一间隔件连接到第一浮栅的边缘并由与第一浮栅相同的导电材料制成。控制门靠近浮动栅极设置。

9. 发明授权

US06849489B2 Method for forming transistors with ultra-short gate feature 有权
标题翻译：用于形成具有超短栅极特性的晶体管的方法
公开(公告)号：US06849489B2
公开(公告)日：2005-02-01
申请号：US10861116
申请日：2004-06-03
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/335 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L21/8247 , H01L27/088 , H01L27/092 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/823418 , H01L21/823468 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： A gate electrode is formed over but is insulated from a semiconductor body region for each of first and second transistors. Off-set spacers are formed along side-walls of the gate electrode of each of the first and second transistors. After forming the off-set spacers, a DDD implant is performed to form DDD source and DDD drain regions in the body region for the first transistor. After the DDD implant, main spacers are formed adjacent the off-set spacers of at least the first transistor. A LDD implant is performed to form LDD source and LDD drain regions for the second transistor. After forming the main spacers, a source/drain (S/D) implant is carried out to form a highly doped region within each of the DDD drain and DDD source regions and each of the LDD drain and LDD source regions.
摘要翻译：在第一和第二晶体管中的每一个上形成栅电极，但是与半导体本体区域绝缘。偏置间隔物沿着第一和第二晶体管的每一个的栅电极的侧壁形成。在形成偏置间隔物之后，执行DDD注入以在第一晶体管的体区中形成DDD源和DDD漏极区。在DDD植入之后，主隔离层邻近至少第一晶体管的偏置间隔物形成。执行LDD注入以形成用于第二晶体管的LDD源极和LDD漏极区域。在形成主间隔物之后，进行源极/漏极（S / D）注入以在每个DDD漏极和DDD源极区域以及LDD漏极和LDD源极区域中的每一个内形成高掺杂区域。

10. 发明授权

US07160774B2 Method of forming polysilicon layers in non-volatile memory 有权
标题翻译：在非易失性存储器中形成多晶硅层的方法
公开(公告)号：US07160774B2
公开(公告)日：2007-01-09
申请号：US10870285
申请日：2004-06-16
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L21/336
CPC分类号： H01L29/4916 , H01L21/28273 , H01L29/42324 , H01L29/7883
摘要： In accordance with an embodiment of the present invention, a semiconductor structure includes an undoped polysilicon layer, a doped polysilicon layer in contact with the undoped polysilicon layer, and an insulating layer in contact with the undoped polysilicon layer. The undoped polysilicon layer is sandwiched between the doped polysilicon layer and the insulating layer.
摘要翻译：根据本发明的实施例，半导体结构包括未掺杂多晶硅层，与未掺杂多晶硅层接触的掺杂多晶硅层，以及与未掺杂多晶硅层接触的绝缘层。未掺杂的多晶硅层夹在掺杂多晶硅层和绝缘层之间。

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