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1. 发明授权

US07154141B2 Source side programming 有权
公开(公告)号：US07154141B2
公开(公告)日：2006-12-26
申请号：US09777007
申请日：2001-02-02
申请人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
发明人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/10
摘要： A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.

2. 发明授权

US5882985A Reduction of field oxide step height during semiconductor fabrication 失效
标题翻译：在半导体制造期间减小场氧化物步长
公开(公告)号：US5882985A
公开(公告)日：1999-03-16
申请号：US541927
申请日：1995-10-10
申请人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
发明人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： A method for reducing the steep step at the edge of a locally oxidized, field oxide boundary region as a result of using the local oxidation of silicon (LOCOS) method to isolate the active regions of a semiconductor wafer. The reduction is carried out by applying a planarizing layer to the field oxide layer and then etching back the planarizing layer and field oxide layer to a desired thickness.
摘要翻译：作为使用硅的局部氧化（LOCOS）方法的局部氧化的场氧化物边界区域的边缘处的陡峭步骤的方法来隔离半导体晶片的有源区域的方法。通过将平坦化层施加到场氧化物层，然后将平坦化层和场氧化物层回蚀刻到期望的厚度来进行还原。

3. 发明授权

US5920506A Method and apparatus for bulk preprogramming flash memory cells with minimal source and drain currents 失效
标题翻译：用于批量预编程具有最小源极和漏极电流的闪存单元的方法和装置
公开(公告)号：US5920506A
公开(公告)日：1999-07-06
申请号：US938389
申请日：1997-09-26
申请人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
发明人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
IPC分类号： G11C16/10 , G11C16/16 , G11C16/04
CPC分类号： G11C16/107 , G11C16/10 , G11C16/16 , G11C2216/16
摘要： Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.
摘要翻译：提供了设备以便于批量预编程闪速存储器或闪速存储器的子块中的每个单元的处理。在该过程中，要预编程的每个单元的源极和漏极被偏置，使得电流不需要在源极和漏极之间通过电池的沟道区域流动，以在电池的沟道区域和电池的浮动栅极之间传输电荷。在具体实施例中，源极和漏极在没有任何特定偏置电压的情况下保持浮置，并且单元的控制栅极被设置在衬底上方9到12伏之间并保持在大约10毫秒（ms）。在替代实施例中，要预编程的所有单元的源极和漏极被偏置到相同的电位，其是负电压，接地或正电压。

4. 发明授权

US5831901A Method of programming a memory cell to contain multiple values 失效
标题翻译：将存储单元编程为包含多个值的方法
公开(公告)号：US5831901A
公开(公告)日：1998-11-03
申请号：US745596
申请日：1996-11-08
申请人： Yuan Tang , Qimeng Zhou , Hsingya Arthur Wang
发明人： Yuan Tang , Qimeng Zhou , Hsingya Arthur Wang
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C2211/5625
摘要： A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.
摘要翻译：公开了一种在单个闪速存储器单元中编程多个值的方法。通过将对应于特定存储器单元的位线保持为Vd来编程单个闪存单元，同时存储单元的控制栅极Vg上的电压变化。通过改变控制栅极上的电压，多个值被存储在存储单元中。所得到的值是自收敛的，因此，验证电路变得不必要。

5. 发明授权

US06490203B1 Sensing scheme of flash EEPROM 失效
标题翻译：闪存EEPROM的检测方案
公开(公告)号：US06490203B1
公开(公告)日：2002-12-03
申请号：US09863697
申请日：2001-05-24
申请人： Yuan Tang
发明人： Yuan Tang
IPC分类号： G11C1604
CPC分类号： G11C16/345 , G11C16/28 , G11C16/3409 , G11C16/3436 , G11C16/3445 , G11C16/3459
摘要： There is provided a reading circuit and method for performing program verify, erase verify, and over-erase-correction verify modes of operations on a selected memory core cell in an array of Flash EEPROM memory core cells. A fixed control gate bias voltage is applied to the control gate of a core cell transistor whose state is to be verified for generating a core cell drain current. Varied control gate bias voltages are applied to the control gate of a single reference cell transistor for generating different reference currents corresponding to predetermined modes of operations. In a second embodiment, the different reference currents are generated from a current source.
摘要翻译：提供了一种用于在闪存EEPROM存储器核心单元阵列中的选定的存储器核心单元上执行程序验证，擦除验证和过擦除校正验证模式的读取电路和方法。将固定的控制栅极偏置电压施加到其状态将被验证以产生核心单元漏极电流的核心单元晶体管的控制栅极。各种控制栅极偏置电压被施加到单个参考单元晶体管的控制栅极，用于产生对应于预定操作模式的不同参考电流。在第二实施例中，从电流源产生不同的参考电流。

6. 发明授权

US06172915B2 Unified erase method in flash EEPROM 有权
标题翻译：闪存EEPROM中的统一擦除方法
公开(公告)号：US06172915B2
公开(公告)日：2001-01-09
申请号：US09408705
申请日：1999-09-30
申请人： Yuan Tang , James C. Yu , Jeffrey W. Anthony
发明人： Yuan Tang , James C. Yu , Jeffrey W. Anthony
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C8/12
摘要： A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time and a uniform VT distribution as good as that of a single-sector erase operation is provided. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector beginning with a first address of each sector if its corresponding erase-on signal is not turned OFF. The current address of each sector is stored at a point where the erase-verify operation failed. An erase pulse is applied only to all sectors simultaneously that have not passed the erase-verify operation. The erase-verify operation is then repeated beginning at the current address stored. The erasing operation is terminated when the erase-on signal has been turned OFF in all sectors in the plurality of sectors.
摘要翻译：在用于执行单扇区，多扇区或全扇区擦除操作的闪存EEPROM存储器单元阵列中使用的统一擦除方法，其具有减少的总擦除时间量和均匀的VT分布与单扇区擦除操作一样好。如果其对应的擦除信号没有关闭，则从第一扇区到最后扇区的多个扇区中顺序执行擦除验证操作，从每个扇区的第一地址开始。每个扇区的当前地址存储在擦除验证操作失败的点。擦除脉冲仅对未通过擦除验证操作的所有扇区同时施加。然后从存储的当前地址开始重复擦除验证操作。当在多个扇区的所有扇区中已经关闭了擦除信号时，结束擦除操作。

7. 发明授权

US5869385A Selectively oxidized field oxide region 失效
标题翻译：选择性氧化场氧化物区域
公开(公告)号：US5869385A
公开(公告)日：1999-02-09
申请号：US569704
申请日：1995-12-08
申请人： Yuan Tang , Mark Ramsbey
发明人： Yuan Tang , Mark Ramsbey
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/76213 , Y10S148/138 , Y10S438/964
摘要： A field oxide region is formed with a reduced bird's beak by selectively implanting impurity atoms into the semiconductor substrate to increase the oxidation rate of the substrate and thermally oxidizing the implanted region of the semiconductor substrate. In another embodiment, a gate oxide layer having a differential thickness is formed by implanting impurity atoms into the semiconductor substrate in a selected region wherein a thick portion of the gate oxide is to be formed and thermally oxidizing the semiconductor substrate.
摘要翻译：通过选择性地将杂质原子注入到半导体衬底中以增加衬底的氧化速率并对半导体衬底的注入区域进行热氧化，形成具有缩小的鸟嘴的场氧化物区域。在另一个实施例中，通过在要形成栅极氧化物的厚部分并对半导体衬底进行热氧化的选定区域中将杂质原子注入到半导体衬底中，形成具有差分厚度的栅氧化层。

8. 发明授权

US5629893A System for constant field erasure in a flash EPROM 失效
标题翻译：闪存EPROM中的常量字段擦除系统
公开(公告)号：US5629893A
公开(公告)日：1997-05-13
申请号：US634512
申请日：1996-04-18
申请人： Yuan Tang , Chi Chang , James C. Yu
发明人： Yuan Tang , Chi Chang , James C. Yu
IPC分类号： G11C16/14 , G11C13/00
CPC分类号： G11C16/14
摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.
摘要翻译：公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。在这样做时，可以以最小的压力擦除FLASH EPROM单元。此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

9. 发明授权

US5481494A Method for tightening VT distribution of 5 volt-only flash EEPROMS 失效
标题翻译：用于紧固5伏特闪光灯的VT分布的方法
公开(公告)号：US5481494A
公开(公告)日：1996-01-02
申请号：US362346
申请日：1994-12-22
申请人： Yuan Tang , Lee E. Cleveland
发明人： Yuan Tang , Lee E. Cleveland
IPC分类号： G11C16/16 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3468
摘要： There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage V.sub.T distribution after erase is obtained without sacrificing any reduction in the erase speed.
摘要翻译：提供了一种用于紧固闪存EEPROM器件中擦除单元的控制栅极阈值电压分布的改进方法。在整个擦除周期期间，将相对低的正电压施加到EEPROM器件的源极区域。施加到EEPROM器件的控制栅极的负的恒定电压的大小在整个擦除周期期间降低到预定的电压电平，以便获得更严格的阈值电压分布。耦合在低正电压和源极区之间的负载电阻器的值同时减小到预定值，以便补偿由负的恒定电压的幅度的降低引起的增加的擦除时间。结果，在擦除之后获得改善的阈值电压VT分布，而不牺牲擦除速度的任何降低。

10. 发明授权

US06680257B2 Alternative related to SAS in flash EEPROM 失效
标题翻译：与闪存EEPROM中的SAS相关的备选方案
公开(公告)号：US06680257B2
公开(公告)日：2004-01-20
申请号：US09916877
申请日：2001-07-30
申请人： Yuan Tang
发明人： Yuan Tang
IPC分类号： H01L21302
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method of eliminating contamination of tunnel oxide in stacked gates due to SAS photoresist process and preventing of n+ implantation caused by resist residue from the SAS photoresist process in fabricating of semiconductor memory devices is disclosed. The process provides for providing stacked gates separated by trenches on the semiconductor memory device. Source and drain implants are performed on the semiconductor memory device before the SAS etch is accomplished. The trenches between the stacked gates are filled with oxide so as to cover the entire surface of the semiconductor memory device prior to applying a SAS photoresist mask. Then, a SAS photoresist mask is applied to a flat top surface of the semiconductor memory device. A SAS etch is performed on the semiconductor memory device so as to remove the oxide. By filling in the trenches with oxide prior to applying the SAS photoresist mask, the possibility of SAS photoresist contamination of the tunnel oxide in the stacked gate has been eliminated. Further, no SAS photoresist residue is left which can block a subsequent n+ doping.
摘要翻译：公开了一种通过SAS光致抗蚀剂工艺消除堆叠栅极中的隧道氧化物的污染的方法，并且防止了在半导体存储器件的制造中由SAS光致抗蚀剂工艺引起的抗蚀剂残留引起的n +注入。该方法提供了在半导体存储器件上提供由沟槽分开的层叠栅极。在完成SAS蚀刻之前，在半导体存储器件上进行源极和漏极注入。层叠栅极之间的沟槽填充有氧化物，以便在施加SAS光致抗蚀剂掩模之前覆盖半导体存储器件的整个表面。然后，将SAS光刻胶掩模施加到半导体存储器件的平坦顶表面。在半导体存储器件上执行SAS蚀刻以去除氧化物。在施加SAS光刻胶掩模之前通过用氧化物填充沟槽，已经消除了堆叠栅极中的隧道氧化物的SAS光致抗蚀剂污染的可能性。此外，没有留下可以阻挡随后的n +掺杂的SAS光致抗蚀剂残留物。

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