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1. 发明授权

US5920506A Method and apparatus for bulk preprogramming flash memory cells with minimal source and drain currents 失效
标题翻译：用于批量预编程具有最小源极和漏极电流的闪存单元的方法和装置
公开(公告)号：US5920506A
公开(公告)日：1999-07-06
申请号：US938389
申请日：1997-09-26
申请人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
发明人： Hsingya Arthur Wang , Haike Dong , Jein-Chen Young , Yuan Tang , Aaron Yip , Kenneth Miu
IPC分类号： G11C16/10 , G11C16/16 , G11C16/04
CPC分类号： G11C16/107 , G11C16/10 , G11C16/16 , G11C2216/16
摘要： Apparatus is provided to facilitate the process of bulk preprogramming each of the cells in a flash memory or a subblock of a flash memory. In the process, the source and drain of each cell to be preprogrammed is biased such that current need not be flowing between the source and drain through the cell's channel region for charge to be transferred between the cell's channel region and the cell's floating gate. In a specific embodiment, the sources and drains are left floating without any particular bias voltage and the control gates of the cells are set to between 9 and 12 volts above the substrate and held there for about 10 milliseconds (ms). In an alternate embodiment, the sources and drains of all of the cells to be preprogrammed are biased to the same potential, which is a negative voltage, ground, or a positive voltage.
摘要翻译：提供了设备以便于批量预编程闪速存储器或闪速存储器的子块中的每个单元的处理。在该过程中，要预编程的每个单元的源极和漏极被偏置，使得电流不需要在源极和漏极之间通过电池的沟道区域流动，以在电池的沟道区域和电池的浮动栅极之间传输电荷。在具体实施例中，源极和漏极在没有任何特定偏置电压的情况下保持浮置，并且单元的控制栅极被设置在衬底上方9到12伏之间并保持在大约10毫秒（ms）。在替代实施例中，要预编程的所有单元的源极和漏极被偏置到相同的电位，其是负电压，接地或正电压。

2. 发明授权

US07154141B2 Source side programming 有权
公开(公告)号：US07154141B2
公开(公告)日：2006-12-26
申请号：US09777007
申请日：2001-02-02
申请人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
发明人： Hsingya Arthur Wang , Yuan Tang , Haike Dong , Ming Sang Kwan , Peter Rabkin
IPC分类号： H01L29/788
CPC分类号： H01L29/7885 , G11C16/10
摘要： A flash EEPROM array having a double-diffused source junction that can be used for source side programming. The flash EEPROM array, when programmed from the source side exhibits fast programming rates. Additionally, source side programming of arrays having different physical characteristics (e.g. transistor cell channel length) exhibit tighter program rate distributions than for the same arrays in which drain side programming is used.

3. 发明授权

US6043123A Triple well flash memory fabrication process 失效
标题翻译：三重闪存制造工艺
公开(公告)号：US6043123A
公开(公告)日：2000-03-28
申请号：US863917
申请日：1997-05-27
申请人： Hsingya Arthur Wang , Jein-Chen Young , Ming-Sang Kwan
发明人： Hsingya Arthur Wang , Jein-Chen Young , Ming-Sang Kwan
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546
摘要： A process is described for fabricating an integrated circuit memory in a semiconductor substrate. In the substrate, a first well is formed by introduction of dopant opposite to conductivity of the substrate. Within the first well a second well is formed of conductivity type matching the substrate. The memory cells are fabricated in the second well and have source and drain regions opposite the conductivity type substrate. Each of the first and second wells also includes a region of corresponding conductivity type to enable separate electrical connections to be made to each of the wells.
摘要翻译：描述了在半导体衬底中制造集成电路存储器的过程。在衬底中，通过引入与衬底的导电性相反的掺杂剂形成第一阱。在第一阱内，第二阱由与衬底相匹配的导电类型形成。存储单元被制造在第二阱中并且具有与导电类型衬底相对的源区和漏区。第一和第二孔中的每一个还包括相应导电类型的区域，以使得能够对每个孔进行单独的电连接。

4. 发明授权

US5866467A Method of improving oxide isolation in a semiconductor device 失效
标题翻译：改善半导体器件中的氧化物隔离的方法
公开(公告)号：US5866467A
公开(公告)日：1999-02-02
申请号：US886844
申请日：1997-07-01
申请人： Hsingya Arthur Wang , Jein-Chen Young , Nicholas H. Tripsas
发明人： Hsingya Arthur Wang , Jein-Chen Young , Nicholas H. Tripsas
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76205 , H01L21/7621
摘要： A silicon substrate has patterned thereon a pad oxide layer and a nitride layer. The exposed surface of the silicon substrate is cleaned of residual oxide, and a layer of oxidizable material such as polysilicon is deposit over the resulting structure. The polysilicon layer is anisotropically etched to form spacers on the side of the nitride layer portions, which are also in contact with the silicon substrate, the etching continuing into the silicon substrate. Field oxidation is then undertaken, with the polysilicon spacers being oxidized, as is a portion of the silicon substrate, the spacers causing initial oxidation during field oxide growth to be removed from the sides of the nitride layer portions, so that encroachment of the oxide under the nitride layer portions is avoided.
摘要翻译：硅衬底上形成有衬垫氧化物层和氮化物层。清除硅衬底的暴露表面残留的氧化物，并且在所得结构上沉积一层可氧化材料如多晶硅。各向异性蚀刻多晶硅层，以在与硅衬底接触的氮化物层部分一侧形成间隔物，蚀刻继续进入硅衬底。然后进行场氧化，其中多晶硅间隔物被氧化，如硅衬底的一部分，在场氧化物生长期间引起初始氧化的间隔物从氮化物层部分的侧面去除，使得氧化物侵蚀在避免了氮化物层部分。

5. 发明授权

US5899726A Method of forming oxide isolation in a semiconductor device 失效
标题翻译：在半导体器件中形成氧化物隔离的方法
公开(公告)号：US5899726A
公开(公告)日：1999-05-04
申请号：US891920
申请日：1997-07-14
申请人： Hsingya Arthur Wang , Mark T. Ramsbey , Jein-Chen Young
发明人： Hsingya Arthur Wang , Mark T. Ramsbey , Jein-Chen Young
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： After providing a patterned nitride layer over a patterned layer of oxide in turn disposed on a silicon substrate, a covering layer of oxide or polysilicon is deposited over the resulting structure to contact the substrate to hold the patterned nitride layer portions in position as field oxide is grown. In addition, field oxide growth rate slows at the edges of the nitride layer portions, allowing additional time for field oxide to flow as it is grown, relieving lifting force on the nitride layer portions, and providing an increase in silicon active area between field oxide regions.
摘要翻译：在依次设置在硅衬底上的图案化氧化物层上提供图案化氮化物层之后，在所得结构上沉积氧化物或多晶硅的覆盖层以接触衬底以将图案化的氮化物层部分保持在适当位置，因为场氧化物长大的。此外，场氧化物生长速率在氮化物层部分的边缘处减慢，允许场氧化物在其生长时流动的额外时间，减轻氮化物层部分上的提升力，并且提供场氧化物之间的硅有源面积的增加地区。

6. 发明授权

US5818082A E.sup.2 PROM device having erase gate in oxide isolation region in shallow trench and method of manufacture thereof 失效
标题翻译： E2PROM器件在浅沟槽中的氧化物隔离区域中具有擦除栅极及其制造方法
公开(公告)号：US5818082A
公开(公告)日：1998-10-06
申请号：US610688
申请日：1996-03-04
申请人： Hsingya Arthur Wang , Jein-Chen Young , Darlene Hamilton
发明人： Hsingya Arthur Wang , Jein-Chen Young , Darlene Hamilton
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/78
CPC分类号： H01L27/11517 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： An E.sup.2 PROM device includes a semiconductor body having source and drain regions and a channel region, with a gate oxide over the channel region and a floating gate over the gate oxide. An oxide isolation region contains a doped polysilicon erase gate, so that erasing of the device takes place by electron flow from the floating gate to the erase gate through a thin oxide portion of the oxide isolation region, at a position spaced from the gate oxide. The inclusion of the erase gate in the oxide isolation region results in smaller overall device size than previously achieved.
摘要翻译： E2PROM器件包括具有源极和漏极区域以及沟道区域的半导体本体，沟道区域上具有栅极氧化物，栅极氧化物上方具有浮动栅极。氧化物隔离区域包含掺杂的多晶硅擦除栅极，使得器件的擦除是通过电子从与栅极氧化物隔开的位置通过氧化物隔离区域的氧化物部分从浮动栅极流向擦除栅极而发生的。在氧化物隔离区域中包括擦除栅极导致比先前实现的更小的整体器件尺寸。

7. 发明授权

US5882985A Reduction of field oxide step height during semiconductor fabrication 失效
标题翻译：在半导体制造期间减小场氧化物步长
公开(公告)号：US5882985A
公开(公告)日：1999-03-16
申请号：US541927
申请日：1995-10-10
申请人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
发明人： Hsingya Arthur Wang , Yuan Tang , Ming Sang Kwan
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76202
摘要： A method for reducing the steep step at the edge of a locally oxidized, field oxide boundary region as a result of using the local oxidation of silicon (LOCOS) method to isolate the active regions of a semiconductor wafer. The reduction is carried out by applying a planarizing layer to the field oxide layer and then etching back the planarizing layer and field oxide layer to a desired thickness.
摘要翻译：作为使用硅的局部氧化（LOCOS）方法的局部氧化的场氧化物边界区域的边缘处的陡峭步骤的方法来隔离半导体晶片的有源区域的方法。通过将平坦化层施加到场氧化物层，然后将平坦化层和场氧化物层回蚀刻到期望的厚度来进行还原。

8. 发明授权

US5831901A Method of programming a memory cell to contain multiple values 失效
标题翻译：将存储单元编程为包含多个值的方法
公开(公告)号：US5831901A
公开(公告)日：1998-11-03
申请号：US745596
申请日：1996-11-08
申请人： Yuan Tang , Qimeng Zhou , Hsingya Arthur Wang
发明人： Yuan Tang , Qimeng Zhou , Hsingya Arthur Wang
IPC分类号： G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C2211/5625
摘要： A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V.sub.d, while the voltage on the control gate, V.sub.g, of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.
摘要翻译：公开了一种在单个闪速存储器单元中编程多个值的方法。通过将对应于特定存储器单元的位线保持为Vd来编程单个闪存单元，同时存储单元的控制栅极Vg上的电压变化。通过改变控制栅极上的电压，多个值被存储在存储单元中。所得到的值是自收敛的，因此，验证电路变得不必要。

9. 发明授权

US07250341B2 Flash memory device having poly spacers 失效
标题翻译：具有聚间隔物的闪存器件
公开(公告)号：US07250341B2
公开(公告)日：2007-07-31
申请号：US11100123
申请日：2005-04-05
申请人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
发明人： Hsingya Arthur Wang , Kai-Cheng Chou , Peter Rabkin
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： A non-volatile memory device includes a substrate having a first active region and a second active region. A first floating gate is provided over the first active region and having an edge, the first floating gate being made of a conductive material. A first spacer is connected to the edge of the first floating gate and being made of the same conductive material as that of the first floating gate. A control gate is provided proximate to the floating gate.
摘要翻译：非易失性存储器件包括具有第一有源区和第二有源区的衬底。第一浮动栅极设置在第一有源区上并具有边缘，第一浮栅由导电材料制成。第一间隔件连接到第一浮栅的边缘并由与第一浮栅相同的导电材料制成。控制门靠近浮动栅极设置。

10. 发明授权

US06777741B2 Non-volatile memory cells with selectively formed floating gate 失效
标题翻译：具有选择性形成的浮动栅极的非易失性存储单元
公开(公告)号：US06777741B2
公开(公告)日：2004-08-17
申请号：US10393603
申请日：2003-03-19
申请人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
发明人： Peter Rabkin , Hsingya Arthur Wang , Kai-Cheng Chou
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Non-volatile memory transistors are provided that include a floating gate formed from first and second layers of material such as polysilicon. The second floating gate layer is selectively grown or deposited on top of the first gate layer, eliminating the need to mask for positioning of the second floating gate layer. The memory transistors are separated by isolation regions. The second floating gate layer overlaps portions of the isolation regions to provide a high control gate-to-floating gate coupling ratio. The process enables smaller memory transistors. Floating gate to isolation overlap, and therefore floating gate to floating gate spacing, is controlled by selective deposition or selective epitaxial growth of the second polysilicon layer.
摘要翻译：提供了非易失性存储晶体管，其包括由第一和第二层材料（例如多晶硅）形成的浮置栅极。第二浮栅层选择性地生长或沉积在第一栅极层的顶部上，消除了对第二浮栅层定位的掩模的需要。存储晶体管由隔离区域分隔开。第二浮栅层与隔离区域的一部分重叠以提供高控制栅 - 浮栅耦合比。该过程使更小的存储晶体管。浮栅为隔离重叠，因此浮栅为浮栅间隔，通过第二多晶硅层的选择性沉积或选择性外延生长来控制。

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