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1. 发明申请

US20050112824A1 Method of forming gate oxide layers with multiple thicknesses on substrate 审中-公开
标题翻译：在衬底上形成多个厚度的栅氧化层的方法
公开(公告)号：US20050112824A1
公开(公告)日：2005-05-26
申请号：US10723794
申请日：2003-11-26
申请人： Yu-Chang Jong , Ruey-Hsin Liu , Yi-Chun Lin , Shun-Liang Hsu , Chen-Bau Wu , Kuo-Ming Wu
发明人： Yu-Chang Jong , Ruey-Hsin Liu , Yi-Chun Lin , Shun-Liang Hsu , Chen-Bau Wu , Kuo-Ming Wu
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823462 , H01L21/823481
摘要： A method of forming gate dielectric layers with various thicknesses on a substrate. At least a first active region and a second active region are provided on the substrate. A first thermal oxide layer is formed on the substrate. A blanket dielectric layer with a first thickness is deposited overlying the substrate. The dielectric layer and the underlying first thermal oxide layer on the second active region are removed to expose the substrate. A second thermal oxide layer with a second thickness less than the first thickness is formed on the second active region. A first gate is formed on the dielectric layer on the first active region and a second gate is formed on the second thermal oxide layer on the second active region.
摘要翻译：在基板上形成各种厚度的栅极电介质层的方法。至少第一有源区和第二有源区设置在衬底上。在基板上形成第一热氧化层。具有第一厚度的覆盖介电层沉积在衬底上。去除第二有源区上的电介质层和下面的第一热氧化物层以露出衬底。在第二有源区上形成第二厚度小于第一厚度的第二热氧化层。第一栅极形成在第一有源区上的电介质层上，第二栅极形成在第二有源区上的第二热氧化物层上。

2. 发明授权

US07521741B2 Shielding structures for preventing leakages in high voltage MOS devices 有权
标题翻译：用于防止高压MOS器件泄漏的屏蔽结构
公开(公告)号：US07521741B2
公开(公告)日：2009-04-21
申请号：US11593424
申请日：2006-11-06
申请人： Yu-Chang Jong , Ruey-Hsin Liu , Yueh-Chiou Lin , Shun-Liang Hsu , Chi-Hsuen Chang , Te-Yin Hsia
发明人： Yu-Chang Jong , Ruey-Hsin Liu , Yueh-Chiou Lin , Shun-Liang Hsu , Chi-Hsuen Chang , Te-Yin Hsia
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L29/0653 , H01L29/0692
摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.
摘要翻译：高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

3. 发明申请

US20080001189A1 Shielding structures for preventing leakages in high voltage MOS devices 有权
标题翻译：用于防止高压MOS器件泄漏的屏蔽结构
公开(公告)号：US20080001189A1
公开(公告)日：2008-01-03
申请号：US11593424
申请日：2006-11-06
申请人： Yu-Chang Jong , Ruey-Hsin Liu , Yueh-Chiou Lin , Shun-Liang Hsu , Chi-Hsuen Chang , Te-Yin Hsia
发明人： Yu-Chang Jong , Ruey-Hsin Liu , Yueh-Chiou Lin , Shun-Liang Hsu , Chi-Hsuen Chang , Te-Yin Hsia
IPC分类号： H01L29/76
CPC分类号： H01L29/7834 , H01L29/0653 , H01L29/0692
摘要： A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.
摘要翻译：高压MOS器件包括覆盖衬底的第一高电压阱（HVW）区域，覆盖衬底的第二HVW区域，与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域基板，其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分，所述第一HVNW区域中的绝缘区域，所述第二HVNW区域和所述HVPW区域，在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域，栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。优选地，栅电极和屏蔽图案具有小于约0.4μm的间隔。屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。

4. 发明授权

US07129559B2 High voltage semiconductor device utilizing a deep trench structure 有权
公开(公告)号：US07129559B2
公开(公告)日：2006-10-31
申请号：US10821432
申请日：2004-04-09
申请人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
发明人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
IPC分类号： H01L29/00
CPC分类号： H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/4933 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.

5. 发明授权

US07482662B2 High voltage semiconductor device utilizing a deep trench structure 有权
标题翻译：利用深沟槽结构的高压半导体器件
公开(公告)号：US07482662B2
公开(公告)日：2009-01-27
申请号：US11554368
申请日：2006-10-30
申请人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
发明人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
IPC分类号： H01L27/088
CPC分类号： H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/4933 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.
摘要翻译：半导体器件包括在源极和漏极之间具有源极，漏极和栅极的衬底。源极和漏极都包括第一边缘，并且栅极包括第一部分。第一深沟槽结构位于栅极的第一部分下方并且靠近源极的第一边缘和漏极的第一边缘。

6. 发明申请

US20070187766A1 High Voltage Semiconductor Device Utilizing A Deep Trench Structure 有权
标题翻译：采用深沟槽结构的高压半导体器件
公开(公告)号：US20070187766A1
公开(公告)日：2007-08-16
申请号：US11554368
申请日：2006-10-30
申请人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
发明人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
IPC分类号： H01L29/94
CPC分类号： H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/4933 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.
摘要翻译：半导体器件包括在源极和漏极之间具有源极，漏极和栅极的衬底。源极和漏极都包括第一边缘，并且栅极包括第一部分。第一深沟槽结构位于栅极的第一部分下方并且靠近源极的第一边缘和漏极的第一边缘。

7. 发明申请

US20050224896A1 High voltage semiconductor device utilizing a deep trench structure 有权
标题翻译：利用深沟槽结构的高压半导体器件
公开(公告)号：US20050224896A1
公开(公告)日：2005-10-13
申请号：US10821432
申请日：2004-04-09
申请人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
发明人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
IPC分类号： H01L21/28 , H01L29/06 , H01L29/45 , H01L29/49 , H01L29/51 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/4933 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.
摘要翻译：半导体器件包括在源极和漏极之间具有源极，漏极和栅极的衬底。源极和漏极都包括第一边缘，并且栅极包括第一部分。第一深沟槽结构位于栅极的第一部分下方并且靠近源极的第一边缘和漏极的第一边缘。

8. 发明申请

US20060108641A1 Device having a laterally graded well structure and a method for its manufacture 审中-公开
标题翻译：具有横向分级井结构的装置及其制造方法
公开(公告)号：US20060108641A1
公开(公告)日：2006-05-25
申请号：US10992861
申请日：2004-11-19
申请人： Yu-Chang Jong , Chen-Bau Wu , Ruey-Hsing Liu , Kuo-Ming Wu
发明人： Yu-Chang Jong , Chen-Bau Wu , Ruey-Hsing Liu , Kuo-Ming Wu
IPC分类号： H01L29/76
CPC分类号： H01L21/26513 , H01L29/0638 , H01L29/66681
摘要： Provided are a device and method for its manufacture. In one example, the device includes a semiconductor substrate that includes a well region formed using a first-type dopant. First and second doped regions are formed in the well region using a second-type dopant, and the first and second doped regions are separated from each other by a dielectric isolation feature. A third doped region is formed in the well region using the first-type dopant and positioned under the dielectric isolation feature and between the first doped region and the second doped region. The third doped region has a dopant concentration higher than that of the well region.
摘要翻译：提供了一种用于其制造的装置和方法。在一个示例中，该器件包括半导体衬底，其包括使用第一类型掺杂剂形成的阱区。使用第二类型掺杂剂在阱区中形成第一和第二掺杂区域，并且第一和第二掺杂区域通过介电隔离特征彼此分离。使用第一型掺杂剂在阱区中形成第三掺杂区域，并且位于第一掺杂区域和第二掺杂区域之间。第三掺杂区的掺杂浓度高于阱区的掺杂浓度。

9. 发明申请

US20070267693A1 SUPPRESSION OF HOT-CARRIER EFFECTS USING DOUBLE WELL FOR THIN GATE OXIDE LDMOS EMBEDDED IN HV PROCESS 有权
标题翻译：在高压工艺中嵌入薄壁氧化物LDMOS的双载体效应的抑制
公开(公告)号：US20070267693A1
公开(公告)日：2007-11-22
申请号：US11419685
申请日：2006-05-22
申请人： Hsing-Yi Chien , Yu-Chang Jong , Ruey-Hsin Liu , Te-Yin Hsia
发明人： Hsing-Yi Chien , Yu-Chang Jong , Ruey-Hsin Liu , Te-Yin Hsia
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42364 , H01L29/7816
摘要： A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
摘要翻译：半导体器件包括：第一高电压阱，其具有设置在半导体衬底中的第一掺杂物; 第二高电压阱，具有设置在半导体衬底中的第二掺杂剂，与第一高压阱横向相邻; 具有设置在第二高压井上的第二掺杂剂的低电压阱; 漏极区，其具有设置在所述第一高压阱中的所述第一掺杂物; 具有设置在低压井中的第一掺杂物的源; 以及设置在所述半导体衬底上并且在所述源极和漏极之间的横向的栅极，其中所述栅极包括薄栅极电介质和栅电极。

10. 发明授权

US07608889B2 Lateral diffusion metal-oxide-semiconductor structure 有权
标题翻译：侧向扩散金属氧化物半导体结构
公开(公告)号：US07608889B2
公开(公告)日：2009-10-27
申请号：US11864278
申请日：2007-09-28
申请人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
发明人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/4933 , H01L29/66659
摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.
摘要翻译：横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。因此，浅沟槽隔离的表面低于半导体衬底的表面。可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

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