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    • 2. 发明授权
    • Shielding structures for preventing leakages in high voltage MOS devices
    • 用于防止高压MOS器件泄漏的屏蔽结构
    • US07521741B2
    • 2009-04-21
    • US11593424
    • 2006-11-06
    • Yu-Chang JongRuey-Hsin LiuYueh-Chiou LinShun-Liang HsuChi-Hsuen ChangTe-Yin Hsia
    • Yu-Chang JongRuey-Hsin LiuYueh-Chiou LinShun-Liang HsuChi-Hsuen ChangTe-Yin Hsia
    • H01L29/76
    • H01L29/7834H01L29/0653H01L29/0692
    • A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.
    • 高压MOS器件包括覆盖衬底的第一高电压阱(HVW)区域,覆盖衬底的第二HVW区域,与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板,其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分,所述第一HVNW区域中的绝缘区域,所述第二HVNW区域和所述HVPW区域,在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域,栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地,栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。
    • 3. 发明申请
    • Shielding structures for preventing leakages in high voltage MOS devices
    • 用于防止高压MOS器件泄漏的屏蔽结构
    • US20080001189A1
    • 2008-01-03
    • US11593424
    • 2006-11-06
    • Yu-Chang JongRuey-Hsin LiuYueh-Chiou LinShun-Liang HsuChi-Hsuen ChangTe-Yin Hsia
    • Yu-Chang JongRuey-Hsin LiuYueh-Chiou LinShun-Liang HsuChi-Hsuen ChangTe-Yin Hsia
    • H01L29/76
    • H01L29/7834H01L29/0653H01L29/0692
    • A high-voltage MOS device includes a first high-voltage well (HVW) region overlying a substrate, a second HVW region overlying the substrate, a third HVW region of an opposite conductivity type as that of the first and the second HVW regions overlying the substrate, wherein the HVPW region has at least a portion between the first HVNW region and the second HVNW region, an insulation region in the first HVNW region, the second HVNW region, and the HVPW region, a gate dielectric over and extending from the first HVNW region to the second HVNW region, a gate electrode on the gate dielectric, and a shielding pattern electrically insulated from the gate electrode over the insulation region. Preferably, the gate electrode and the shielding pattern have a spacing of less than about 0.4 μm. The shielding pattern is preferably connected to a voltage lower than a stress voltage applied on the gate electrode.
    • 高压MOS器件包括覆盖衬底的第一高电压阱(HVW)区域,覆盖衬底的第二HVW区域,与覆盖衬底的第一和第二HVW区域相反的导电类型的第三HVW区域 基板,其中所述HVPW区域具有在所述第一HVNW区域和所述第二HVNW区域之间的至少一部分,所述第一HVNW区域中的绝缘区域,所述第二HVNW区域和所述HVPW区域,在所述第一HVNW区域和所述第二HVNW区域之间延伸的栅极电介质 HVNW区域到第二HVNW区域,栅极电介质上的栅极电极以及在绝缘区域上与栅电极电绝缘的屏蔽图案。 优选地,栅电极和屏蔽图案具有小于约0.4μm的间隔。 屏蔽图案优选地连接到低于施加在栅电极上的应力电压的电压。