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1. 发明授权

US5734920A Input/output processing IC 失效
标题翻译：输入/输出处理IC
公开(公告)号：US5734920A
公开(公告)日：1998-03-31
申请号：US835907
申请日：1997-01-10
申请人： Yoshinori Gotoh , Kenji Murakami , Tadashi Shibata , Shunji Kamei , Hajime Nomura
发明人： Yoshinori Gotoh , Kenji Murakami , Tadashi Shibata , Shunji Kamei , Hajime Nomura
IPC分类号： G06F13/12 , G06F7/00
CPC分类号： G06F13/124
摘要： A compact input/output processing IC, which reduces the CPU load, to which microcomputer 100, input/output processing IC 200, and various inputs and outputs are connected. Parallel signals are connected to a high-speed input/output buffer and serial signals are connected from communications control circuit 207 via serial communications circuit 206 to SIO 104. To achieve the proper control, data requiring high speed is handled by parallel communications. Serial communications is handled by shift registers, first bit of each being connected to the last bit of the other, to form a loop, with instruction and input/output data from the CPU exchanged simultaneously, thereby achieving efficient processing. This achieves better organization of the communications for input/output processing, enabling both better control and a compact hardware design.
摘要翻译：将微型计算机100，输入/输出处理IC 200以及各种输入和输出连接到的小型输入/输出处理IC，其减少CPU负载。并行信号连接到高速输入/输出缓冲器，并且串行信号从通信控制电路207通过串行通信电路206连接到SIO 104.为了实现适当的控制，需要高速的数据通过并行通信来处理。串行通信由移位寄存器处理，每一个的第一位被连接到另一个的最后一位，以形成一个循环，来自CPU的指令和输入/输出数据被同时交换，从而实现有效的处理。这可以更好地组织输入/输出处理的通信，从而实现更好的控制和紧凑的硬件设计。

2. 发明申请

US20100182339A1 DATA PROCESSING APPARATUS AND METHOD 审中-公开
标题翻译：数据处理装置和方法
公开(公告)号：US20100182339A1
公开(公告)日：2010-07-22
申请号：US12668180
申请日：2008-05-28
申请人： Nobutaka Kitajima , Akira Tanaka , Tadashi Shibata
发明人： Nobutaka Kitajima , Akira Tanaka , Tadashi Shibata
IPC分类号： G09G5/00 , G06K9/36
CPC分类号： H04N5/91 , G11B20/10527 , G11B27/3036 , G11B2020/10629 , G11B2020/10675 , G11B2020/10712 , G11B2020/10759 , G11B2220/2541 , H04N9/8042 , H04N9/8205 , H04N9/8227 , H04N19/44
摘要： A stream processing section (12) analyzes input stream data and, if the stream data includes a compressed/coded graphics object, decodes the graphics object line by line and writes the decoded graphics object into a graphics object buffer (14), and, if the stream data includes control information of a graphics object, writes the control information into a control information buffer (13). A graphics control section (15) renders a graphics object stored in the graphics object buffer (14) in a graphics plane (16) based on control information stored in the control information buffer (13). When a decoding error has occurred, the stream processing section (12) restarts decoding from the next or a subsequent line.
摘要翻译：流处理部分（12）分析输入流数据，并且如果流数据包括压缩/编码图形对象，逐行解码图形对象，并将解码的图形对象写入图形对象缓冲器（14）中，并且如果流数据包括图形对象的控制信息，将控制信息写入控制信息缓冲器（13）。图形控制部分（15）基于存储在控制信息缓冲器（13）中的控制信息，在图形平面（16）中呈现存储在图形对象缓冲器（14）中的图形对象。当发生解码错误时，流处理部分（12）从下一行或后续行重新开始解码。

3. 发明授权

US07382171B2 Semiconductor circuit for detecting a signal propagation time 有权
标题翻译：用于检测信号传播时间的半导体电路
公开(公告)号：US07382171B2
公开(公告)日：2008-06-03
申请号：US10779802
申请日：2004-02-18
申请人： Makoto Ogawa , Tadashi Shibata
发明人： Makoto Ogawa , Tadashi Shibata
IPC分类号： H03H11/26
CPC分类号： H03K5/13 , G06K9/62
摘要： There is provided a semiconductor circuit including three or more nodes at least including one input node and one output node, plural paths which are connected between the three or more nodes and whose signal propagation directions between the nodes are regulated, a signal propagation time regulator for regulating a signal propagation time of each of the paths, an input unit for inputting a predetermined input signal to the input node, and a detector for detecting a time required for the input signal to propagate through the paths and arrive at the output node.
摘要翻译：提供了包括三个或更多个节点的半导体电路，至少包括一个输入节点和一个输出节点，连接在三个或更多个节点之间的多个路径，并且其节点之间的信号传播方向被调节，信号传播时间调节器调节每个路径的信号传播时间，用于向输入节点输入预定输入信号的输入单元，以及检测器，用于检测输入信号通过路径传播并到达输出节点所需的时间。

4. 发明申请

US20050250883A1 Tire 有权
标题翻译：胎
公开(公告)号：US20050250883A1
公开(公告)日：2005-11-10
申请号：US10526466
申请日：2003-09-01
申请人： Tadashi Shibata , Eiji Nakamura , Hirofumi Aoki
发明人： Tadashi Shibata , Eiji Nakamura , Hirofumi Aoki
IPC分类号： B60C1/00 , C08K5/11 , C08L1/00
CPC分类号： C08K5/11 , B60C1/00 , B60C1/0016 , B60C11/005 , C08K3/013 , C08K5/25 , Y02T10/862 , C08K3/0033 , C08L21/00
摘要： The present invention relates to a tire characterized by using as a member, a rubber composition comprising (a) a rubber component comprising at least one selected from a natural rubber and a diene base synthetic rubber, (b) silica having a nitrogen-absorbing specific surface area (N2SA) of 180 to 270 m2/g and 0.1 to 10.0 mass parts of (c) a partial ester compound of maleic anhydride and a (poly)oxypropylene derivative per 100 mass parts of the rubber component described above. Further, the present invention relates to a tire characterized by using as a tread rubber, a rubber composition comprising (A) a rubber component comprising a conjugate diene base rubber, (B) a filler comprising 10 mass % or more of a white filler based on the whole fillers and (C) a partial ester compound of maleic anhydride and a (poly)oxypropylene derivative. According to the present invention, capable of being obtained is a tire in which an abrasion resistance and a low heat build-up property are enhanced while improving a processability thereof without causing a reduction in the physical properties of a rubber composition and a problem on a working environment or a tire which is excellent in both of a driving stability and a wet gripping property.
摘要翻译：本发明涉及一种轮胎，其特征在于，使用橡胶组合物作为构件，所述橡胶组合物包含（a）包含选自天然橡胶和二烯基合成橡胶中的至少一种的橡胶组分，（b）具有吸氮特性表面积（N 2 S SA）为180〜270μm2 / g，0.1〜10.0质量份（c）马来酸酐的偏酯化合物和（聚）氧亚丙基衍生物/ 100质量份上述橡胶组分。此外，本发明涉及一种轮胎，其特征在于使用胎面橡胶，橡胶组合物，其包含（A）包含共轭二烯基橡胶的橡胶组分，（B）包含10质量％以上的白色填料的填料（C）马来酸酐和（聚）氧丙烯衍生物的偏酯化合物。根据本发明，能够获得耐磨性和低发热性提高同时提高其加工性而不引起橡胶组合物的物理性能降低的轮胎，工作环境或在驱动稳定性和湿抓地性都优异的轮胎。

5. 发明授权

US06459312B2 Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop 失效
标题翻译：半导体集成电路，具有相同电路的延迟锁定环路，自同步管线型系统，压控振荡器和锁相环
公开(公告)号：US06459312B2
公开(公告)日：2002-10-01
申请号：US09919926
申请日：2001-08-02
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： H03L700
CPC分类号： H03K3/0315 , H03K3/354 , H03K5/133 , H03K2005/00045 , H03L7/0812 , H03L7/0995 , H03L2207/06
摘要： The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.
摘要翻译：通过其中信号输入端子通过第一电容器连接到读出放大器的输入端的电路来解决抖动量增加与延迟量增加的问题，控制输入端子通过第二电容器连接到输入端读出放大器的端子和读出放大器的输入端与第一和第二电容器之间的公共连接点是浮动节点，并且其中通过信号输入端施加到读出放大器的输入端的信号是垂直的至少在感测放大器的判定阈值附近，施加到控制输入端子的控制信号移位，从而控制输出的延迟量。

6. 发明授权

US6127852A Semiconductor integrated circuit for parallel signal processing 失效
标题翻译：半导体集成电路并行信号处理
公开(公告)号：US6127852A
公开(公告)日：2000-10-03
申请号：US110014
申请日：1998-07-02
申请人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
发明人： Katsuhisa Ogawa , Tadahiro Ohmi , Tadashi Shibata
IPC分类号： G01D1/12 , G06G7/12 , G06G7/122 , H01L21/8238 , H01L27/092 , H01L29/78 , H03D1/00
CPC分类号： G06G7/122
摘要： To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the other terminal side of the second capacitive means.
摘要翻译：为了通过最大或最小位置检测并行信号处理电路以高精度检索模拟信号，通过第一电容装置将晶体管的栅极连接到信号输入端的多个电路单元中的多个电路单元，栅极和第一电容装置连接到第二电容装置的一个端子侧，以及控制装置，用于使第二电容装置的另一个端子侧的电压波动，以进一步增加或减少对应于在第二电容装置的漏极和另一个端子侧之间连接漏极电流的增加或减少，多个电路单元中的每个晶体管的源极共同连接并连接到恒定电流源，并且执行相对于施加到每个信号输入端子的信号电压的最大或最小电压位置检测通过第二电容装置的另一个端子侧的电压。

7. 发明授权

US6115725A Semiconductor arithmetic apparatus 失效
标题翻译：半导体运算装置
公开(公告)号：US6115725A
公开(公告)日：2000-09-05
申请号：US14644
申请日：1998-01-28
申请人： Tadashi Shibata , Tadahiro Ohmi , Akira Nataka , Tatsuo Morimoto , Masahiro Konda
发明人： Tadashi Shibata , Tadahiro Ohmi , Akira Nataka , Tatsuo Morimoto , Masahiro Konda
IPC分类号： G06T9/00 , H03M7/30 , G06F7/00 , H04N7/12
CPC分类号： H03M7/3082 , G06T9/008 , H04N19/94
摘要： The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed. In the operating system, which is provided with a first mechanism (202), comprising a plurality of groups of numerical values, a second mechanism (201), a first circuit (206), a second circuit (206), and a third circuit (210), the second circuit comprises a plurality of fourth circuits divided into two or more groups (210-213, 219, and 301), the fourth circuits have a plurality of input terminals and at least one output terminal, and a mechanism is provided having a structure wherein various signals expressing degrees of similarity are inputted into the plurality of input terminals, only that signal having the largest degree of similarity among the variety of signals expressing degrees of similarity which are inputted is outputted from the output terminal, and the output signal of a predetermined first group among the two or more groups is inputted into an input terminal of a second group, whereby only one first vector having the largest degree of similarity is selected.
摘要翻译：使用矢量量化的运动图像的实时压缩是使用简单的硬件和相对于所采用的通信线路容量的最佳压缩比来实现的。在具有第一机构（202）的操作系统中，包括多组数值，第二机构（201），第一电路（206），第二电路（206）和第三电路（210），所述第二电路包括分成两组或更多组（210-213,219和301）的多个第四电路，所述第四电路具有多个输入端子和至少一个输出端子，并且机构是具有这样的结构，其中表示相似度的各种信号被输入到多个输入端，只有表示输入的相似度的各种信号之间具有最大相似程度的信号从输出端输出，将两个以上组中的预定第一组的输出信号输入到第二组的输入端，由此仅选择具有最大相似度的一个第一矢量。

8. 发明授权

US5939925A Semiconductor circuitry to process analog signals using weighted- sum operations 失效
标题翻译：半导体电路，用加权和运算处理模拟信号
公开(公告)号：US5939925A
公开(公告)日：1999-08-17
申请号：US930508
申请日：1997-11-07
申请人： Tadashi Shibata , Tadahiro Ohmi , Ning Mei Yu , Tsutomu Nakai
发明人： Tadashi Shibata , Tadahiro Ohmi , Ning Mei Yu , Tsutomu Nakai
IPC分类号： G06F17/16 , G06J1/00 , G06K9/64 , G06G7/12
CPC分类号： G06K9/64 , G06F17/16 , G06J1/00
摘要： A semiconductor operational circuit conducts real-time analog vector operations to permit the determination of the center of gravity of an image of a moving object. The circuit employs a first processing stage utilizing CMOS source follower circuits to perform weighted linear sum operations on the analog signals. A second processing stage utilizes comparator circuitry to perform comparison operations involving data from the weighted-sum and non-weighted-sum operations. A third processing stage utilizes exclusive OR gates to provide digital data outputs based on the comparison operation results.
摘要翻译： PCT No.PCT / JP96 / 00883 Sec。 371日期：1997年11月7日 102（e）日期1997年11月7日PCT 1996年4月1日PCT PCT。出版物WO96 / 30827 日期1996年10月3日半导体运算电路进行实时模拟矢量运算，以确定移动物体的图像的重心。电路采用利用CMOS源极跟随器电路的第一处理级，对模拟信号执行加权线性和运算。第二处理阶段利用比较器电路执行涉及来自加权和和非加权和运算的数据的比较运算。第三处理级利用异或门来提供基于比较运算结果的数字数据输出。

9. 发明授权

US5683072A Thin film forming equipment 失效
标题翻译：薄膜成型设备
公开(公告)号：US5683072A
公开(公告)日：1997-11-04
申请号：US508405
申请日：1995-07-31
申请人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
发明人： Tadahiro Ohmi , Tadashi Shibata , Masaru Umeda
IPC分类号： C23C8/14 , C23C14/34 , C23C14/35 , C23C14/56 , C23C16/44 , F16K31/02 , F16K51/02 , H01J37/32 , F16K3/18
CPC分类号： H01J37/32174 , C23C14/34 , C23C14/35 , C23C14/56 , C23C14/564 , C23C16/4404 , C23C8/14 , F16K31/02 , F16K51/02 , H01J37/32082 , H01J2237/186
摘要： A gate valve for a thin film forming apparatus. The gate valve includes two adjoining low-pressure chambers and a wall separating the two chambers. The wall includes an aperture and a thin plate for covering the aperture. The thin plate is movable in a direction substantially parallel to the plate surface. The gate valve further includes a voltage supply for applying a direct current between the thin plate and the wall.
摘要翻译：一种用于薄膜形成装置的闸阀。闸阀包括两个相邻的低压室和分隔两个室的壁。该壁包括孔和用于覆盖孔的薄板。薄板可以在基本上平行于板表面的方向上移动。闸阀还包括用于在薄板和壁之间施加直流电的电压源。

10. 发明授权

US5592015A Dielectric isolated type semiconductor device provided with bipolar element 失效
标题翻译：具有双极元件的绝缘隔离型半导体器件
公开(公告)号：US5592015A
公开(公告)日：1997-01-07
申请号：US547740
申请日：1995-10-26
申请人： Makio Iida , Tadashi Shibata , Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
发明人： Makio Iida , Tadashi Shibata , Takayuki Sugisaka , Shoji Miura , Toshio Sakakibara
IPC分类号： H01L29/73 , H01L21/331 , H01L21/762 , H01L21/763 , H01L27/02 , H01L29/732 , H01L29/00 , H01L23/58
CPC分类号： H01L29/7322 , H01L21/76264 , H01L21/763 , H01L27/0248 , H01L21/76286
摘要： A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.
摘要翻译：提供一种半导体器件，其使得高耐压双极晶体管变小，并防止晶体管的开关速度的劣化。在硅衬底上形成硅氧化物层，在氧化硅层上形成由隔离沟侧向隔离的一种导电型半导体岛。在半导体岛的外周部形成有氧化硅膜，以埋置沟槽。在半导体岛中，形成双极晶体管，即另一种导电型的基极区域，在基极区域形成一个导电型的发射极区域，并进一步形成一种导电型的集电极区域。在半导体岛中，进一步形成用于提取施加恒定电位的过量载流子的另一导电类型的扩散区域。

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