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    • 1. 发明申请
    • IMAGE PROCESSING APPARATUS AND METHOD
    • 图像处理装置和方法
    • US20080252750A1
    • 2008-10-16
    • US12099563
    • 2008-04-08
    • Katsuhisa Ogawa
    • Katsuhisa Ogawa
    • H04N5/235
    • H04N5/243H04N5/23232H04N5/23245
    • An image processing apparatus can determine a correction gain factor at a high rate of speed to synthesize an image. The image processing apparatus includes a long second middle luminance image detecting unit for detecting a pixel position of a pixel having a pixel value in a first middle luminance pixel value region from the long second exposure image, a short second middle luminance image detecting unit for detecting a pixel position of a pixel having a pixel value in second middle luminance pixel value region from the short second exposure image; a correction gain factor calculating unit for designating, as a common pixel, a pixel having a common pixel position such that the pixel position detected by the long second middle luminance image detecting unit is the same as the pixel position detected by the short second middle luminance image detecting unit, and for calculating a correction gain factor based on the pixel value of the long second exposure image and the pixel value of the short second exposure image at a pixel position of the common pixel position.
    • 图像处理装置可以以高速率确定校正增益因子以合成图像。 该图像处理装置包括:长的第二中间亮度图像检测单元,用于检测来自长第二曝光图像的第一中间亮度像素值区域中具有像素值的像素的像素位置;短第二中间亮度图像检测单元,用于检测 具有来自短第二曝光图像的第二中间亮度像素值区域中的像素值的像素的像素位置; 校正增益因子计算单元,用于指定具有公共像素位置的像素作为公共像素,使得由第二中间亮度图像检测单元检测的像素位置与由短的第二中间亮度检测到的像素位置相同 图像检测单元,并且用于基于长第二曝光图像的像素值和公共像素位置的像素位置处的短第二曝光图像的像素值来计算校正增益因子。
    • 9. 发明授权
    • Semiconductor integrated circuit for parallel signal processing
    • 半导体集成电路并行信号处理
    • US6127852A
    • 2000-10-03
    • US110014
    • 1998-07-02
    • Katsuhisa OgawaTadahiro OhmiTadashi Shibata
    • Katsuhisa OgawaTadahiro OhmiTadashi Shibata
    • G01D1/12G06G7/12G06G7/122H01L21/8238H01L27/092H01L29/78H03D1/00
    • G06G7/122
    • To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the other terminal side of the second capacitive means.
    • 为了通过最大或最小位置检测并行信号处理电路以高精度检索模拟信号,通过第一电容装置将晶体管的栅极连接到信号输入端的多个电路单元中的多个电路单元, 栅极和第一电容装置连接到第二电容装置的一个端子侧,以及控制装置,用于使第二电容装置的另一个端子侧的电压波动,以进一步增加或减少对应于 在第二电容装置的漏极和另一个端子侧之间连接漏极电流的增加或减少,多个电路单元中的每个晶体管的源极共同连接并连接到恒定电流源,并且 执行相对于施加到每个信号输入端子的信号电压的最大或最小电压位置检测 通过第二电容装置的另一个端子侧的电压。