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1. 发明申请

US20050141262A1 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US20050141262A1
公开(公告)日：2005-06-30
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： H01L27/108 , G11C11/24 , G11C11/404 , H01L21/8239 , H01L21/8242 , H01L21/84 , H01L27/105 , H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

2. 发明授权

US06778424B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06778424B2
公开(公告)日：2004-08-17
申请号：US09986777
申请日：2001-11-09
申请人： Yoshihisa Iwata , Takashi Ohsawa , Takashi Yamada
发明人： Yoshihisa Iwata , Takashi Ohsawa , Takashi Yamada
IPC分类号： G11C1124
CPC分类号： H01L29/7841 , G11C11/404 , G11C11/4085 , G11C11/4087 , G11C2211/4016 , H01L23/544 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having MIS transistors to constitute memory cells (MC), each of the MIS transistors including a semiconductor layer (12), a source region (15) formed in the semiconductor layer, a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (13) provided between the source region and the drain region to form a channel in the channel body; and an auxiliary gate (20) provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate. The MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.
摘要翻译：一种具有构成存储单元（MC）的MIS晶体管的半导体存储器件，每个所述MIS晶体管包括半导体层（12），形成在所述半导体层中的源极区（15），形成在所述半导体层源极区域，位于源极区域和用作浮动状态的沟道体的漏极区域之间的半导体层，设置在源极区域和漏极区域之间的主栅极（13），以在沟道中形成沟道身体; 以及与主门分开设置的辅助门（20），以通过电容耦合来控制通道体的电位，辅助门与主门同步地驱动。 MIS晶体管具有第一数据状态，其中通道主体被设置在第一电位和第二数据状态，其中通道主体被设置在第二电位。

3. 发明授权

US07075820B2 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US07075820B2
公开(公告)日：2006-07-11
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

4. 发明授权

US06548848B2 Semiconductor memory device 失效
公开(公告)号：US06548848B2
公开(公告)日：2003-04-15
申请号：US10005180
申请日：2001-12-03
申请人： Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Takashi Yamada
发明人： Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Takashi Yamada
IPC分类号： H01L27108
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10841 , H01L27/1203 , H01L29/7841
摘要： Each of MIS transistors of a semiconductor memory device has a semiconductor layer (12); a source region (15) formed in the semiconductor layer; a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate (13) which forms a channel in the channel body; a second gate (20) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region (21) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.

5. 发明授权

US09608526B2 DC/DC converter, on-board unit and charging device 有权
公开(公告)号：US09608526B2
公开(公告)日：2017-03-28
申请号：US14371682
申请日：2012-04-27
申请人： Susumu Okura , Takashi Ohsawa
发明人： Susumu Okura , Takashi Ohsawa
IPC分类号： H02M3/335 , B60Q1/30 , B60L11/18 , H02J5/00
CPC分类号： H02M3/33507 , B60L11/1811 , B60L2210/10 , B60Q1/30 , H02J5/005 , H02J7/025 , H02J50/12 , H02M3/33576
摘要： A DC/DC converter 1 is configured to allow separation of a primary side constitution unit 3 and a secondary side constitution unit 4 of a transformer 2. A secondary side switching element FET 2 is provided in the secondary side constitution unit 4, and controls power supply to a load 12 by intermitting an output of a secondary winding L2. The primary side constitution unit 3 detects an electrical behavior of the primary side generated by the intermittent operation of the secondary side, and controls the power supplied from the primary winding L1 to the secondary winding L2 by operating the intermittent operation of the primary side switching element FET 1 such that a cycle or duty of the intermittent operation of the secondary side falls within a predetermined range.

6. 发明授权

US09125263B2 LED lighting device 有权
标题翻译： LED照明装置
公开(公告)号：US09125263B2
公开(公告)日：2015-09-01
申请号：US14004876
申请日：2011-08-05
申请人： Norikazu Tateishi , Takashi Ohsawa
发明人： Norikazu Tateishi , Takashi Ohsawa
IPC分类号： H05B41/00 , H05B33/08
CPC分类号： H05B33/0815 , H05B33/0809 , H05B33/0821 , H05B33/0827 , H05B33/083
摘要： An LED lighting device 1 lights LED blocks 4a and 4b which correspond to a plurality of functions of an illuminator such as headlights and are connected in series. The LED blocks 4a and 4b are connected in series with a current converting unit 5. While the LED blocks 4a and 4b are supplied with a current Ia from a single DC/DC converter unit 3, the LED block 4b is supplied with a current Ib that passes through conversion by the current converting unit 5 and that differs from the current Ia the DC/DC converter unit 3 outputs. Thus, the LED blocks 4a and 4b are each lit with appropriate brightness.
摘要翻译： LED照明装置1照亮与块灯等照明装置的多个功能对应的LED块4a，4b，并串联连接。 LED块4a和4b与电流转换单元5串联连接。当LED块4a和4b从单个DC / DC转换器单元3被提供有电流Ia时，向LED块4b提供电流Ib 其通过当前转换单元5的转换，并且与DC / DC转换器单元3输出的电流Ia不同。因此，LED块4a和4b分别以适当的亮度点亮。

7. 发明申请

US20140368167A1 DC/DC CONVERTER, ON-BOARD UNIT AND CHARGING DEVICE 有权
标题翻译： DC / DC转换器，板上单元和充电装置
公开(公告)号：US20140368167A1
公开(公告)日：2014-12-18
申请号：US14371682
申请日：2012-04-27
申请人： Susumu Okura , Takashi Ohsawa
发明人： Susumu Okura , Takashi Ohsawa
IPC分类号： H02M3/335 , B60Q1/30 , B60L11/18
CPC分类号： H02M3/33507 , B60L11/1811 , B60L2210/10 , B60Q1/30 , H02J5/005 , H02J7/025 , H02J50/12 , H02M3/33576
摘要： A DC/DC converter 1 is configured to allow separation of a primary side constitution unit 3 and a secondary side constitution unit 4 of a transformer 2. A secondary side switching element FET 2 is provided in the secondary side constitution unit 4, and controls power supply to a load 12 by intermitting an output of a secondary winding L2. The primary side constitution unit 3 detects an electrical behavior of the primary side generated by the intermittent operation of the secondary side, and controls the power supplied from the primary winding L1 to the secondary winding L2 by operating the intermittent operation of the primary side switching element FET 1 such that a cycle or duty of the intermittent operation of the secondary side falls within a predetermined range.
摘要翻译： DC / DC转换器1被配置为允许分离变压器2的初级侧构造单元3和次级侧构造单元4.次级侧开关元件FET2设置在次级侧构成单元4中，并且控制功率通过间接二次绕组L2的输出来供给到负载12。初级侧构成单元3检测由次级侧的间歇动作产生的一次侧的电气行为，并且通过操作初级侧开关元件的间歇动作来控制从初级绕组L1向次级绕组L2供给的电力 FET 1，使得次级侧的间歇动作的周期或占空比落在预定范围内。

8. 发明授权

US08575839B2 Headlamp LED lighting apparatus and vehicle headlamp lighting system 有权
标题翻译：前照灯LED照明装置和车灯前照灯系统
公开(公告)号：US08575839B2
公开(公告)日：2013-11-05
申请号：US13381876
申请日：2009-09-10
申请人： Yu Inoue , Takashi Ohsawa
发明人： Yu Inoue , Takashi Ohsawa
IPC分类号： B60Q1/04
CPC分类号： H05B33/0893
摘要： A headlamp LED lighting apparatus, which lights an LED block 2 having a plurality of LEDs connected in series, samples the output voltage of the headlamp LED lighting apparatus, calculates the average voltage during every prescribed interval, and has a storage unit for storing the average voltage during every prescribed interval calculated. A control circuit 8 compares the voltage variation in the average voltage during every prescribed interval read out of the storage unit with a prescribed threshold, and decides an LED failure of the LED block 2 from a result of the comparison.
摘要翻译：照亮具有串联连接的多个LED的LED块2的前照灯LED照明装置对前照灯LED照明装置的输出电压进行采样，计算每个规定间隔期间的平均电压，并具有用于存储平均值的存储单元计算每个规定间隔期间的电压。控制电路8将从存储单元读出的每个规定间隔期间的平均电压的电压变化与规定的阈值进行比较，并根据比较结果判定LED块2的LED故障。

9. 发明申请

US20130027173A1 TRANSFORMER 审中-公开
标题翻译：变压器
公开(公告)号：US20130027173A1
公开(公告)日：2013-01-31
申请号：US13639171
申请日：2010-07-26
申请人： Takashi Ohsawa
发明人： Takashi Ohsawa
IPC分类号： H01F27/28
CPC分类号： H01F27/325 , H01F27/2852 , H01F27/306
摘要： A columnar leg portion 54 of a first core 50 is inserted into a tubular portion 21 of a second bobbin 20 having a secondary winding 40 wound therearound and including a flange 22 at one end, and the columnar leg portion 54 of the first core 50 and the tubular portion 21 of the second bobbin 20 are inserted into a tubular portion 11 of a first bobbin 10 having a primary winding 30 wound therearound and having a flange 12 at one end, and a leading end 41 as the wind-beginning of the secondary winding 40 is pulled out to the outside of a transformer through the gap between the tubular portions 11 and 21.
摘要翻译：第一芯50的柱状腿部54插入到具有卷绕在其周围的次级绕组40的第二线轴20的管状部分21中，并且在一端包括凸缘22，并且在第一芯50的柱状腿部54和第二绕线筒20的管状部分21插入到第一线轴10的管状部分11中，第一线轴10具有卷绕在其上的初级绕组30，并且在一端具有凸缘12，并且作为次级的起始端的前端41 绕组40通过管状部分11和21之间的间隙被拉出到变压器的外部。

10. 发明授权

US08174920B2 Semiconductor memory device and driving method of the same 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08174920B2
公开(公告)日：2012-05-08
申请号：US12711613
申请日：2010-02-24
申请人： Fumiyoshi Matsuoka , Takashi Ohsawa
发明人： Fumiyoshi Matsuoka , Takashi Ohsawa
IPC分类号： G11C7/02 , G11C11/24
CPC分类号： G11C11/4091 , G11C11/4076 , G11C2207/002 , G11C2207/005 , G11C2211/4016
摘要： A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch circuit latching data to the 1st and 2nd-SN; a first data line (DQ) from the 1st-SN to outside; and a 2nd-DQ from the 2nd-SN to outside, wherein write data is transmitted from the 1st and 2nd-DQ to the 1st and 2nd-SN corresponding to selected cells before the 1st and 2nd-TG are set to be a conductive state, when writing data into the selected cells to be written out of the cells, and write data in the 1st and 2nd-SN corresponding to the selected cells are started to be written into the selected cells, when the 1st and 2nd-TG are set to be a conductive state.
摘要翻译：存储器包括第一和第二位线（BL）; 第一和第二感测节点（SN）; 第一个BL和第一个SN之间的第一个传输门; 在第二BL和第二-SN之间的第二传输门（TG）; 锁存电路将数据锁存到第1和第2-SN; 第一个数据线（DQ）从第一个SN到外部; 以及从第2-SN到外部的第2-DQ，其中在将第1和第2 -TT设置为导通状态之前，将写入数据从第1和第2-DQ发送到对应于所选择的单元的第1和第2-SN 当将数据写入要被写入单元格的所选单元格中时，开始将与所选单元相对应的第1和第2-SN中的写入数据写入所选单元格，当设置第1和第2 -TG时成为导电状态。

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