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1. 发明授权

US07978552B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07978552B2
公开(公告)日：2011-07-12
申请号：US12564526
申请日：2009-09-22
申请人： Fumiyoshi Matsuoka , Takashi Ohsawa
发明人： Fumiyoshi Matsuoka , Takashi Ohsawa
IPC分类号： G11C7/02
CPC分类号： G11C11/404 , G11C8/10 , G11C11/4097 , G11C2211/4016
摘要： A memory includes memory cells, wherein during a first write operation in which first logical data is written in all memory cells connected to a first word line, a source line driver and a word line driver, the source line driver shifts a voltage of a selected source line corresponding to the first word line in a direction away from the voltage of the first word line and the word line driver shifts a voltage of a second word line in a same direction as a transition direction of voltage of a selected source line, and during a second write operation in which second logical data is written in a selected cell connected to the first word line, the source line driver and the word line driver shift voltages of the selected source line and the second word line in a direction approaching the voltage of the first word line.
摘要翻译：存储器包括存储器单元，其中在第一写入操作期间，其中第一逻辑数据被写入连接到第一字线的所有存储单元，源极线驱动器和字线驱动器中，源极线驱动器将所选择的电压源极线与远离第一字线的电压的方向对应于第一字线，并且字线驱动器沿与所选择的源极线的电压的转变方向相同的方向移位第二字线的电压，并且在第二写入操作期间，第二逻辑数据被写入连接到第一字线的所选单元中，源极线驱动器和字线驱动器在接近电压的方向上移动所选择的源极线和第二字线的电压的第一个字线。

2. 发明申请

US20100238740A1 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20100238740A1
公开(公告)日：2010-09-23
申请号：US12711613
申请日：2010-02-24
申请人： Fumiyoshi Matsuoka , Takashi Ohsawa
发明人： Fumiyoshi Matsuoka , Takashi Ohsawa
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4076 , G11C2207/002 , G11C2207/005 , G11C2211/4016
摘要： A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch circuit latching data to the 1st and 2nd-SN; a first data line (DQ) from the 1st-SN to outside; and a 2nd-DQ from the 2nd-SN to outside, wherein write data is transmitted from the 1st and 2nd-DQ to the 1st and 2nd-SN corresponding to selected cells before the 1st and 2nd-TG are set to be a conductive state, when writing data into the selected cells to be written out of the cells, and write data in the 1st and 2nd-SN corresponding to the selected cells are started to be written into the selected cells, when the 1st and 2nd-TG are set to be a conductive state.
摘要翻译：存储器包括第一和第二位线（BL）; 第一和第二感测节点（SN）; 第一个BL和第一个SN之间的第一个传输门; 在第二BL和第二-SN之间的第二传输门（TG）; 锁存电路将数据锁存到第1和第2-SN; 第一个数据线（DQ）从第一个SN到外部; 以及从第2-SN到外部的第2-DQ，其中在将第1和第2 -TT设置为导通状态之前，将写入数据从第1和第2-DQ发送到对应于所选择的单元的第1和第2-SN 当将数据写入要被写入单元格的所选单元格中时，开始将与所选单元相对应的第1和第2-SN中的写入数据写入所选单元格，当设置第1和第2 -TG时成为导电状态。

3. 发明授权

US08174920B2 Semiconductor memory device and driving method of the same 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US08174920B2
公开(公告)日：2012-05-08
申请号：US12711613
申请日：2010-02-24
申请人： Fumiyoshi Matsuoka , Takashi Ohsawa
发明人： Fumiyoshi Matsuoka , Takashi Ohsawa
IPC分类号： G11C7/02 , G11C11/24
CPC分类号： G11C11/4091 , G11C11/4076 , G11C2207/002 , G11C2207/005 , G11C2211/4016
摘要： A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch circuit latching data to the 1st and 2nd-SN; a first data line (DQ) from the 1st-SN to outside; and a 2nd-DQ from the 2nd-SN to outside, wherein write data is transmitted from the 1st and 2nd-DQ to the 1st and 2nd-SN corresponding to selected cells before the 1st and 2nd-TG are set to be a conductive state, when writing data into the selected cells to be written out of the cells, and write data in the 1st and 2nd-SN corresponding to the selected cells are started to be written into the selected cells, when the 1st and 2nd-TG are set to be a conductive state.
摘要翻译：存储器包括第一和第二位线（BL）; 第一和第二感测节点（SN）; 第一个BL和第一个SN之间的第一个传输门; 在第二BL和第二-SN之间的第二传输门（TG）; 锁存电路将数据锁存到第1和第2-SN; 第一个数据线（DQ）从第一个SN到外部; 以及从第2-SN到外部的第2-DQ，其中在将第1和第2 -TT设置为导通状态之前，将写入数据从第1和第2-DQ发送到对应于所选择的单元的第1和第2-SN 当将数据写入要被写入单元格的所选单元格中时，开始将与所选单元相对应的第1和第2-SN中的写入数据写入所选单元格，当设置第1和第2 -TG时成为导电状态。

4. 发明授权

US07088617B2 Nonvolatile semiconductor storage device, and liquid crystal display device including the same 有权
标题翻译：非易失性半导体存储装置以及包含该非易失性半导体存储装置的液晶显示装置
公开(公告)号：US07088617B2
公开(公告)日：2006-08-08
申请号：US10919777
申请日：2004-08-16
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii
IPC分类号： G11C16/04
CPC分类号： G11C16/0483
摘要： A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the respective memory cell unit groups are each uniquely selected on the basis of a combination of the common control gate line and the first and second common selection gate lines.
摘要翻译：一种非易失性半导体存储装置，包括：多个存储单元单元组，每个存储单元单元组包括一个或多个NAND非易失性存储单元单元，每个非易失性存储单元单元包括至少一个具有控制栅极的存储单元，晶体管具有第二选择栅极，所述存储单元单元组还包括连接到所述控制栅极的控制栅极线，连接到所述第一选择栅极的第一选择栅极线和连接到所述第二选择栅极的第二选择栅极线; 公共控制栅极线，共同地连接到不同的存储单元单元组的控制栅极线; 第一公共选择栅极线，共同连接到不同的存储单元单元组的第一选择栅极线; 以及第二公共选择栅极线，共同连接到不同的存储单元单元组的第二选择栅极线; 其中各个存储单元单元组中的存储单元是基于公共控制栅极线和第一和第二公共选择栅极线的组合而被唯一地选择的。

5. 发明授权

US08476931B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08476931B2
公开(公告)日：2013-07-02
申请号：US13306760
申请日：2011-11-29
申请人： Fumiyoshi Matsuoka
发明人： Fumiyoshi Matsuoka
IPC分类号： H03K19/0175
CPC分类号： H03K19/00361 , H03K19/017581
摘要： A semiconductor device includes a core circuit including an integrated circuit; output drivers, each including sub-drivers to output digital data transferred from the core circuit, as output data; and a selector that selects a sub-driver to be driven from among the plurality of sub-drivers. Each of the sub-drivers includes: an output transistor connected between a first power supply and an output wiring line to allow the output data to rise or fall according to the digital data; and a switching transistor and a slew-rate control transistor which are connected in series between a gate of the output transistor and a second power supply. The switching transistor turns on or off the output transistor according to the digital data. A gate potential adjusted to determine a slew rate for rise or fall of the output data is selectively provided by the selector to each slew-rate control transistor.
摘要翻译：半导体器件包括：集成电路的核心电路; 输出驱动器，每个包括用于输出从核心电路传送的数字数据的子驱动器作为输出数据; 以及选择器，其从所述多个子驱动器中选择要驱动的子驱动器。每个子驱动器包括：输出晶体管，连接在第一电源和输出布线之间，以允许输出数据根据数字数据上升或下降; 以及串联连接在输出晶体管的栅极和第二电源之间的开关晶体管和摆率控制晶体管。开关晶体管根据数字数据导通或关断输出晶体管。由选择器选择性地为每个转换速率控制晶体管提供调整以确定输出数据的上升或下降的转换速率的栅极电位。

6. 发明授权

US07387935B2 Memory cell unit, nonvolatile semiconductor storage device including memory cell unit, and memory cell array driving method 有权
标题翻译：存储单元单元，包括存储单元单元的非易失性半导体存储器件和存储单元阵列驱动方法
公开(公告)号：US07387935B2
公开(公告)日：2008-06-17
申请号：US10941505
申请日：2004-09-14
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno , Ryusuke Matsuyama , Shinji Horii , Takuji Tanigami
IPC分类号： H01L21/336 , G11C16/04
CPC分类号： H01L29/7926 , G11C16/0483 , H01L27/115 , H01L27/11556 , H01L29/7881 , H01L29/792
摘要： A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part of a channel region provided in the peripheral wall of the column-shaped semiconductor layer in opposed relation to the gate electrode of the selection transistor.
摘要翻译：一种存储单元，包括：在其表面的至少一部分中具有源极扩散层的半导体衬底; 设置在半导体基板上的柱状半导体层，在其最上部设置有漏极扩散层，在底部设置有第一低浓度杂质扩散层; 存储单元布置，其包括设置在所述列状半导体层的周壁中并且与所述基板垂直串联连接的多个存储单元，所述存储单元各自具有电荷存储层和控制栅极; 设置在所述存储单元布置的下端的第二杂质扩散层; 以及选择晶体管，其具有设置在所述柱状半导体层的周壁周围的栅电极，并且连接所述第二杂质扩散层和所述第一杂质扩散层; 其中所述第一杂质扩散层延伸到与所述选择晶体管的栅电极相对的所述柱状半导体层的周壁中设置的沟道区的一部分。

7. 发明申请

US20080079473A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080079473A1
公开(公告)日：2008-04-03
申请号：US11864041
申请日：2007-09-28
申请人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
发明人： Fumiyoshi Matsuoka , Yohji Watanabe , Ryo Fukuda
IPC分类号： H03K3/356
CPC分类号： H03K3/356191 , H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.
摘要翻译：第二导电型晶体管包括由形成在第一导电型半导体层上的第二导电型扩散层形成的源极和漏极; 并且通过绝缘膜夹在第二导电型扩散层之间的第一导电型半导体层上形成的栅极第一导电型晶体管包括由形成的第一导电型扩散层形成的源极和漏极在第二导电型半导体层上; 以及形成在通过绝缘膜夹在第一导电型扩散层之间的第二导电型半导体层上的栅极。用于构造第二导电型晶体管的第二导电型扩散层被分成多个区域，每个区域被形成在第一导电型半导体层上的器件隔离区分隔开。用于构造第一导电型晶体管的第一导电型扩散层被分成多个区域，每个区域被形成在第二导电类型半导体层上的器件隔离区隔开。

8. 发明申请

US20050051806A1 Memory cell unit, nonvolatile semiconductor device, and liquid crystal display device including the nonvolatile semiconductor device 审中-公开
标题翻译：存储单元单元，非易失性半导体器件和包括非易失性半导体器件的液晶显示器件
公开(公告)号：US20050051806A1
公开(公告)日：2005-03-10
申请号：US10930229
申请日：2004-08-30
申请人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno
发明人： Fujio Masuoka , Hiroshi Sakuraba , Fumiyoshi Matsuoka , Syounosuke Ueno
IPC分类号： G02F1/133 , H01L21/8247 , H01L27/115 , H01L29/768 , H01L29/786 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11556 , H01L27/115
摘要： A memory cell unit including: a semiconductor substrate having a source diffusion layer provided in a surface thereof; a column-shaped semiconductor layer provided on the source diffusion layer and having a drain diffusion layer provided in an uppermost portion thereof; a memory cell arrangement which includes a plurality of memory cells arranged in series with the intervention of a first impurity diffusion layer; a first selection transistor connected to one end of the memory cell arrangement with the intervention of a second impurity diffusion layer and connected to the drain diffusion layer; and a second selection transistor connected to the other end of the memory cell arrangement with the intervention of a third impurity diffusion layer and connected to the source diffusion layer; wherein a distance between the third impurity diffusion layer and the source diffusion layer is greater than a distance between impurity diffusion layers disposed on opposite sides of each of the memory cells, whereby punch-through of the second selection transistor is prevented when a writing prevention voltage is applied between the source diffusion layer and the first impurity diffusion layer.
摘要翻译：一种存储单元，包括：具有设置在其表面中的源极扩散层的半导体衬底; 设置在源极扩散层上并具有设置在其最上部的漏极扩散层的柱状半导体层; 存储单元布置，其包括与第一杂质扩散层的介入串联布置的多个存储单元; 连接到所述存储单元布置的一端的第一选择晶体管，其具有第二杂质扩散层并连接到所述漏极扩散层; 以及第二选择晶体管，其连接到所述存储单元布置的另一端，并具有第三杂质扩散层并连接到所述源极扩散层; 其中所述第三杂质扩散层和所述源极扩散层之间的距离大于设置在每个所述存储单元的相对侧上的杂质扩散层之间的距离，从而当写入防止电压施加在源极扩散层和第一杂质扩散层之间。

9. 发明授权

US08811096B2 Output driver circuit and semiconductor storage device 有权
标题翻译：输出驱动电路和半导体存储器件
公开(公告)号：US08811096B2
公开(公告)日：2014-08-19
申请号：US13607090
申请日：2012-09-07
申请人： Fumiyoshi Matsuoka
发明人： Fumiyoshi Matsuoka
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1069 , G11C11/4093
摘要： An output driver circuit includes an on/off-timing control circuit that outputs first and second driving signals based on an input data signal, such that the transition of the second driving signal is faster than the transition of the first driving signal when the input data signal transitions from high level to low level, and the transition of the second driving signal is slower than the transition of the first driving signal when the input data signal transitions from low level to high level. The output driver circuit is further provided with pull-down and pull-up pre-drivers that output pull-down and pull-up signals, respectively, in accordance with the first and second driving signals. The output driver circuit is further provided with pull-down and pull-up main drivers that pull down and pull up the voltage of an output terminal, respectively, in accordance with the pull-down signal and the pull-up signal.
摘要翻译：输出驱动器电路包括基于输入数据信号输出第一和第二驱动信号的开/关定时控制电路，使得当输入数据时第二驱动信号的转变比第一驱动信号的转变快信号从高电平转换到低电平，并且当输入数据信号从低电平转变到高电平时，第二驱动信号的转变比第一驱动信号的转变慢。输出驱动电路还具有根据第一和第二驱动信号分别输出下拉和上拉信号的下拉和上拉预驱动器。输出驱动器电路还具有根据下拉信号和上拉信号分别下拉和上拉输出端的电压的下拉和上拉主驱动器。

10. 发明授权

US08405432B2 Output buffer circuit, input buffer circuit, and input/output buffer circuit 有权
标题翻译：输出缓冲电路，输入缓冲电路，输入/输出缓冲电路
公开(公告)号：US08405432B2
公开(公告)日：2013-03-26
申请号：US12963114
申请日：2010-12-08
申请人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
发明人： Masaru Koyanagi , Yasufumi Kajiyama , Ryo Fukuda , Fumiyoshi Matsuoka , Yasuhiro Suematsu
IPC分类号： H03K3/01
CPC分类号： H03K19/00384 , H03K19/01721
摘要： An output buffer circuit in accordance with an embodiment comprises a plurality of buffer circuits, each of the buffer circuits including a transistor operative to change an output signal of an output terminal in response to a change in an input signal, the output buffer circuit being configured to enable the plurality of buffer circuits to be driven selectively. Each of the plurality of buffer circuits includes a plurality of output transistors having respective current paths formed in parallel to one another between a fixed voltage terminal supplying a certain fixed voltage and an output terminal, and being selectively rendered in an operable state in accordance with a control signal provided from external. The plurality of output transistors included in each of the plurality of buffer circuits are formed having a certain size ratio.
摘要翻译：根据实施例的输出缓冲器电路包括多个缓冲电路，每个缓冲电路包括一个晶体管，用于响应于输入信号的变化而改变输出端的输出信号，该输出缓冲电路被配置以使得能够选择性地驱动多个缓冲电路。多个缓冲电路中的每一个包括多个输出晶体管，其具有在提供一定固定电压的固定电压端子和输出端子之间彼此并联形成的各自的电流路径，并且根据控制信号由外部提供。包含在多个缓冲电路的每一个中的多个输出晶体管形成为具有一定的尺寸比。

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