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1. 发明申请

US20050141262A1 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US20050141262A1
公开(公告)日：2005-06-30
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： H01L27/108 , G11C11/24 , G11C11/404 , H01L21/8239 , H01L21/8242 , H01L21/84 , H01L27/105 , H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

2. 发明授权

US07075820B2 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US07075820B2
公开(公告)日：2006-07-11
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

3. 发明授权

US06548848B2 Semiconductor memory device 失效
公开(公告)号：US06548848B2
公开(公告)日：2003-04-15
申请号：US10005180
申请日：2001-12-03
申请人： Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Takashi Yamada
发明人： Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Takashi Yamada
IPC分类号： H01L27108
CPC分类号： G11C11/404 , G11C2211/4016 , H01L27/108 , H01L27/10802 , H01L27/10823 , H01L27/10841 , H01L27/1203 , H01L29/7841
摘要： Each of MIS transistors of a semiconductor memory device has a semiconductor layer (12); a source region (15) formed in the semiconductor layer; a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate (13) which forms a channel in the channel body; a second gate (20) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region (21) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.

4. 发明授权

US06778424B2 Semiconductor memory device and method of manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06778424B2
公开(公告)日：2004-08-17
申请号：US09986777
申请日：2001-11-09
申请人： Yoshihisa Iwata , Takashi Ohsawa , Takashi Yamada
发明人： Yoshihisa Iwata , Takashi Ohsawa , Takashi Yamada
IPC分类号： G11C1124
CPC分类号： H01L29/7841 , G11C11/404 , G11C11/4085 , G11C11/4087 , G11C2211/4016 , H01L23/544 , H01L27/108 , H01L27/10802 , H01L27/10844 , H01L27/1203 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device having MIS transistors to constitute memory cells (MC), each of the MIS transistors including a semiconductor layer (12), a source region (15) formed in the semiconductor layer, a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (13) provided between the source region and the drain region to form a channel in the channel body; and an auxiliary gate (20) provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate. The MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.
摘要翻译：一种具有构成存储单元（MC）的MIS晶体管的半导体存储器件，每个所述MIS晶体管包括半导体层（12），形成在所述半导体层中的源极区（15），形成在所述半导体层源极区域，位于源极区域和用作浮动状态的沟道体的漏极区域之间的半导体层，设置在源极区域和漏极区域之间的主栅极（13），以在沟道中形成沟道身体; 以及与主门分开设置的辅助门（20），以通过电容耦合来控制通道体的电位，辅助门与主门同步地驱动。 MIS晶体管具有第一数据状态，其中通道主体被设置在第一电位和第二数据状态，其中通道主体被设置在第二电位。

5. 发明授权

US5043298A Process for manufacturing a DRAM cell 失效
标题翻译：用于制造DRAM单元的工艺
公开(公告)号：US5043298A
公开(公告)日：1991-08-27
申请号：US619666
申请日：1990-11-28
申请人： Takashi Yamada , Fumio Horiguchi , Satoshi Inoue , Akihiro Nitayama , Kazumasa Sunouchi
发明人： Takashi Yamada , Fumio Horiguchi , Satoshi Inoue , Akihiro Nitayama , Kazumasa Sunouchi
IPC分类号： H01L27/04 , H01L21/28 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417
CPC分类号： H01L27/10808
摘要： When a semiconductor device having a multi-layered contact is fabaricated, the gate electrode is covered with a thick insulator film. A polycrystalline silicon film is formed in a state in which at least the gate electrode in the contact forming area is covered with a first oxidization-proof insulator film. An inter-layer insulator film is then formed in a state in which at least part of the polycrystalline silicon film is covered with a second oxidization-proof insulator film. A first contact hole is formed using the polycrystalline silicon film as an etching stopper, and the polycrystalline silicon film is then oxidized. Furthermore, a second contact hole is formed in the inter-layer insulator film on the upper surface of the second oxidization-proof insulator film using as the etching stopper the polycrystalline silicon film underlying the second oxidization-proof insulator film. Since the polycrystalline silicon film is formed under the inter-layer insulator film in the second contact forming area so as to cover the gate electrode, it acts as a stopper when the second contact is formed to thereby prevent a short circuit with the gate electrode even if there is no distance between the gate electrode and the second contact.
摘要翻译：当具有多层接触的半导体器件被制造时，栅电极被厚绝缘膜覆盖。在至少形成接触形成区域中的栅电极被第一耐氧化绝缘膜覆盖的状态下形成多晶硅膜。然后在至少部分多晶硅膜被第二防氧化绝缘膜覆盖的状态下形成层间绝缘膜。使用多晶硅膜作为蚀刻阻挡层形成第一接触孔，然后将多晶硅膜氧化。此外，在第二耐氧化绝缘膜的上表面上的层间绝缘膜中形成第二接触孔，使用作为蚀刻停止层的第二耐氧化绝缘膜的下面的多晶硅膜。由于在第二接触形成区域中的层间绝缘体膜下方形成多晶硅膜以覆盖栅电极，所以当形成第二接触时，其作为阻挡体，从而防止栅电极的短路甚至如果栅电极和第二触点之间没有距离。

6. 发明授权

US5488242A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5488242A
公开(公告)日：1996-01-30
申请号：US156931
申请日：1993-11-24
申请人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
发明人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/68 , H01L29/92
CPC分类号： H01L27/10829
摘要： In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.
摘要翻译：在具有通过形成在存储单元区域中的沟槽中的绝缘膜形成存储节点电极从而形成电容器的结构的DRAM中，并且其中存储节点电极连接在源极/漏极区域 MOSFET通过形成在绝缘膜的一部分中的存储节点接触，沟槽设置成在MOSFET的沟道区域中宽度偏离，使得相邻元件区域之间的距离减小，而不会导致在形成存储节点接触，从而提供小型化的高可靠性DRAM。此外，存储节点接触和沟槽可以形成为大尺寸。

7. 发明授权

US08965146B2 Advanced-format optical modulator with low power consumption and low-loss characteristics 有权
标题翻译：高级格式的光调制器具有低功耗和低损耗特性
公开(公告)号：US08965146B2
公开(公告)日：2015-02-24
申请号：US13381298
申请日：2010-07-09
申请人： Takashi Goh , Yoshiyuki Doi , Shinji Mino , Ken Tsuzuki , Hiroshi Yamazaki , Takashi Yamada
发明人： Takashi Goh , Yoshiyuki Doi , Shinji Mino , Ken Tsuzuki , Hiroshi Yamazaki , Takashi Yamada
IPC分类号： G02F1/035 , G02F1/03 , G02F1/225 , G02B6/12
CPC分类号： G02F1/0327 , G02B2006/12142 , G02B2006/12159 , G02F1/225 , G02F2201/126 , G02F2203/20 , G02F2203/21
摘要： In a nest MZI modulator in which each arm includes a child MZI, the power consumption is reduced. The hybrid integrated-type nest MZI modulator of the embodiment 1a is configured so that, instead of placing a relative phase adjusting section in a parent MZI, a bias electrode Bias 90° in which an electric field is applied in the same direction to the polarization direction in both of the upper and lower arms is placed in each child MZI (see FIG. 4B). The bias electrode Bias 90° provided in each child MZI constitute the entirety of a relative phase adjusting section. The optical signals are subjected to a phase change after the output from the child MZI (see FIG. 1A), because such relative phase adjusting section can subject the optical signals of the upper and lower arms of the child MZI to a shift change in the same direction, respectively.
摘要翻译：在其中每个臂包括儿童MZI的巢MZI调制器中，功耗降低。实施例1a的混合集成型嵌套MZI调制器被配置为使得不是将相对相位调整部分放置在母MZI中，而是将偏置电极偏置90°，其中向与极化相同的方向施加电场将上臂和下臂两者的方向放置在每个子MZI中（参见图4B）。每个子MZI中设置的偏置电极偏置90°构成相对相位调整部的整体。在从子MZI（参见图1A）的输出之后，光信号经受相变，因为这种相对相位调整部分可以使子MZI的上臂和下臂的光信号在相同方向。

8. 发明申请

US20140015496A1 CHARGING DEVICE 审中-公开
标题翻译：充电设备
公开(公告)号：US20140015496A1
公开(公告)日：2014-01-16
申请号：US13933458
申请日：2013-07-02
申请人： Tadao Nishiguchi , Takashi Yamada , Hideyuki Yasugi , Masayuki Hanatani , Yusaku Ido
发明人： Tadao Nishiguchi , Takashi Yamada , Hideyuki Yasugi , Masayuki Hanatani , Yusaku Ido
IPC分类号： H02J7/00
CPC分类号： H02J7/007 , H02J7/022 , H02M1/42 , H02M3/33507 , H02M2001/007 , H02M2001/4291 , Y02B40/90 , Y02B70/12 , Y02B70/126
摘要： A charging device has an AC power supply input part that rectifies an AC voltage, a power factor correction part that converts a rectified voltage outputted from the AC power supply input part into a DC intermediate voltage, a power conversion part that converts the intermediate voltage outputted from the power factor correction part into a charge voltage, and supplies the charge voltage to a secondary battery, an input voltage acquisition unit that acquires the rectified voltage outputted from the AC power supply input part, an output voltage acquisition unit that acquires the charge voltage outputted from the power conversion part, and a storage part in which the rectified voltage, the charge voltage, and a target intermediate voltage correlated with the rectified voltage and charge voltage are stored.
摘要翻译：充电装置具有对交流电压进行整流的交流电源输入部，将从交流电源输入部输出的整流电压转换为直流中间电压的功率因数校正部，转换输出的中间电压的功率转换部从功率因数校正部变为充电电压，并将充电电压提供给二次电池，获取从交流电源输入部输出的整流电压的输入电压获取单元，获取充电电压的输出电压获取单元以及存储与整流电压和充电电压相关的整流电压，充电电压和目标中间电压的存储部。

9. 发明申请

US20130334879A1 VEHICLE POWER-SUPPLY CONTROL DEVICE 有权
标题翻译：车辆电源控制装置
公开(公告)号：US20130334879A1
公开(公告)日：2013-12-19
申请号：US13917089
申请日：2013-06-13
申请人： Yusaku Ido , Takashi Yamada , Tadao Nishiguchi , Hideyuki Yasugi , Masayuki Hanatani
发明人： Yusaku Ido , Takashi Yamada , Tadao Nishiguchi , Hideyuki Yasugi , Masayuki Hanatani
IPC分类号： B60R16/033
CPC分类号： B60R16/033 , B60L1/00 , B60L1/003 , B60L1/14 , B60L11/1805 , B60L11/1816 , B60L11/1824 , B60L11/1868 , B60L2210/10 , B60L2210/30 , Y02T10/7005 , Y02T10/7066 , Y02T10/7072 , Y02T10/7216 , Y02T10/7241 , Y02T10/92 , Y02T90/121 , Y02T90/127 , Y02T90/14
摘要： A vehicle power-supply control device has a battery charger that converts an externally-supplied AC voltage into a DC voltage used to charge a vehicle high-voltage battery, a low-voltage power generator that converts the DC voltage output from the battery charger into a DC voltage used to drive a vehicle auxiliary machine, and a controller that controls the battery charger and the low-voltage power generator. The battery charger includes a power factor correction circuit that corrects a power factor of the AC voltage and a first DC/DC converter that generates a predetermined DC voltage based on an output of the power factor correction circuit. The low-voltage power generator includes a second DC/DC converter that steps down the DC voltage output from the battery charger and a synchronous rectifier that rectifies an output of the second DC/DC converter in synchronization with a switching operation of the second DC/DC converter.
摘要翻译：车辆电源控制装置具有将外部供给的交流电压转换成用于对车辆用高压电池充电的直流电压的电池充电器，将从电池充电器输出的直流电压转换为低压电力的低压发电机用于驱动车辆辅助机器的DC电压，以及控制电池充电器和低压发电机的控制器。电池充电器包括校正AC电压的功率因数的功率因数校正电路和基于功率因数校正电路的输出产生预定DC电压的第一DC / DC转换器。低压发电机包括：第二DC / DC转换器，其降低从电池充电器输出的直流电压;以及同步整流器，其与第二DC / DC转换器的开关操作同步地整流第二DC / DC转换器的输出; DC转换器。

10. 发明授权

US08610291B2 Copper alloy bonding wire for semiconductor device 有权
标题翻译：用于半导体器件的铜合金接合线
公开(公告)号：US08610291B2
公开(公告)日：2013-12-17
申请号：US11848403
申请日：2007-08-31
申请人： Tomohiro Uno , Keiichi Kimura , Takashi Yamada
发明人： Tomohiro Uno , Keiichi Kimura , Takashi Yamada
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/85 , B23K35/302 , B23K2103/12 , C22C9/00 , H01L24/43 , H01L24/45 , H01L24/48 , H01L2224/05624 , H01L2224/05639 , H01L2224/43 , H01L2224/43848 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/45647 , H01L2224/45663 , H01L2224/45687 , H01L2224/45693 , H01L2224/48227 , H01L2224/48247 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48824 , H01L2224/48839 , H01L2224/48844 , H01L2224/85205 , H01L2224/85439 , H01L2224/85444 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01012 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01052 , H01L2924/01057 , H01L2924/01058 , H01L2924/01059 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/01105 , H01L2924/01204 , H01L2924/01205 , H01L2924/01206 , H01L2924/10253 , H01L2924/20752 , H01L2924/20755 , H01L2924/20756 , H01L2924/01008 , H01L2924/01004 , H01L2924/01013 , H01L2924/01025 , H01L2924/01039 , H01L2924/00015 , H01L2924/00 , H01L2924/013 , H01L2924/00014 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/2011 , H01L2924/20111 , H01L2924/01055 , H01L2924/00013
摘要： The present invention provides a semiconductor-device copper-alloy bonding wire which has an inexpensive material cost, ensures a superior ball joining shape, wire joining characteristic, and the like, and a good loop formation characteristic, and a superior mass productivity. The semiconductor-device copper-alloy bonding wire contains at least one of Mg and P in total of 10 to 700 mass ppm, and oxygen within a range from 6 to 30 mass ppm.
摘要翻译：本发明提供了一种廉价的材料成本的半导体器件铜合金接合线，确保了优异的球接合形状，线接合特性等，并且具有良好的环形成特性，并且具有优异的批量生产率。半导体装置铜合金接合线含有总共10〜700质量ppm的Mg和P中的至少一种，氧在6〜30质量ppm的范围内。

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