专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080258176A1 Antimonide-based compound semiconductor with titanium tungsten stack 有权
标题翻译：锑化合物半导体与钛钨叠层
公开(公告)号：US20080258176A1
公开(公告)日：2008-10-23
申请号：US11788145
申请日：2007-04-18
申请人： Yeong-Chang Chou , Jay Crawford , Jane Lee , Jeffrey Ming-Jer Yang , John Bradley Boos , Nicolas Alexandrou Papanicolaou
发明人： Yeong-Chang Chou , Jay Crawford , Jane Lee , Jeffrey Ming-Jer Yang , John Bradley Boos , Nicolas Alexandrou Papanicolaou
IPC分类号： H01L23/48 , H01L21/3205 , H01L21/335 , H01L31/00
CPC分类号： H01L29/66431 , H01L29/7783
摘要： An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.
摘要翻译：一个实例中的装置包括基于锑化物的化合物半导体（ABCS）堆叠，形成在ABCS堆叠上的上阻挡层和形成在上阻挡层上的栅极堆叠。上阻挡层包括铟，铝和砷。栅堆叠包括形成在上阻挡层上的钛和钨的基层。

2. 发明授权

US08421121B2 Antimonide-based compound semiconductor with titanium tungsten stack 有权
公开(公告)号：US08421121B2
公开(公告)日：2013-04-16
申请号：US11788145
申请日：2007-04-18
申请人： Yeong-Chang Chou , Jay Crawford , Jane Lee , Jeffrey Ming-Jer Yang , John Bradley Boos , Nicolas Alexandrou Papanicolaou
发明人： Yeong-Chang Chou , Jay Crawford , Jane Lee , Jeffrey Ming-Jer Yang , John Bradley Boos , Nicolas Alexandrou Papanicolaou
IPC分类号： H01L29/778
CPC分类号： H01L29/66431 , H01L29/7783
摘要： An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.

3. 发明申请

US20080251891A1 Semiconductor having passivated sidewalls 审中-公开
标题翻译：具有钝化侧壁的半导体
公开(公告)号：US20080251891A1
公开(公告)日：2008-10-16
申请号：US11784872
申请日：2007-04-10
申请人： Yeong-Chang Chou , Peter S. Nam , Chun H. Lin , Augusto Gutierrez , Jeffrey Ming-Jer Yang , Michael Wojtowicz
发明人： Yeong-Chang Chou , Peter S. Nam , Chun H. Lin , Augusto Gutierrez , Jeffrey Ming-Jer Yang , Michael Wojtowicz
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： H01L21/31612 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/3145
摘要： The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor includes the steps of applying a nitride or other protective material over a wafer using PECVD or other appropriate deposition method.
摘要翻译：半导体器件的层具有暴露边缘。易受氧化的层通过用氮化物钝化层涂覆而防止氧化。可以使用等离子体增强化学气相沉积（PECVD）来施加氮化物钝化层。制造钝化侧壁半导体的方法包括以下步骤：使用PECVD或其它合适的沉积方法在晶片上施加氮化物或其它保护材料。

4. 发明授权

US07615863B2 Multi-dimensional wafer-level integrated antenna sensor micro packaging 有权
标题翻译：多维晶圆级集成天线传感器微包装
公开(公告)号：US07615863B2
公开(公告)日：2009-11-10
申请号：US11581851
申请日：2006-10-16
申请人： Jeffrey Ming-Jer Yang , Yun-Ho Chung , Patty Chang-Chien
发明人： Jeffrey Ming-Jer Yang , Yun-Ho Chung , Patty Chang-Chien
IPC分类号： H01L23/34
CPC分类号： H01L23/66 , H01L23/10 , H01L25/16 , H01L2223/6677 , H01L2924/0002 , H01L2924/01079 , H01L2924/1423 , H01Q1/2283 , H01Q3/30 , H01Q13/02 , H01L2924/00
摘要： An integrated packaging assembly for an MMIC that uses the semiconductor wafers on which circuit elements are fabricated as the package. The packaging assembly includes a plurality of semiconductor layers that have been diced from the semiconductor wafers, where the semiconductor layers can be made of different semiconductor material. The semiconductor layers define cavities therebetween in which circuit components are fabricated. A sealing ring seals the semiconductor layers together so as to hermetically seal the circuit components within the cavities.
摘要翻译：一种用于MMIC的集成包装组件，其使用其上制造电路元件的半导体晶片作为封装。包装组件包括已经从半导体晶片切割的多个半导体层，其中半导体层可以由不同的半导体材料制成。半导体层在其间限定了空腔，其中制造了电路部件。密封环将半导体层密封在一起，以便密封腔内的电路元件。

5. 发明授权

US07777318B2 Wafer level packaging integrated hydrogen getter 有权
标题翻译：晶圆级封装集成吸气剂
公开(公告)号：US07777318B2
公开(公告)日：2010-08-17
申请号：US11782460
申请日：2007-07-24
申请人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
发明人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
IPC分类号： H01L23/20
CPC分类号： H01L23/26 , H01L23/053 , H01L23/10 , H01L2924/0002 , H01L2924/1423 , H01L2924/00
摘要： A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.
摘要翻译：晶片级封装，其在晶片级封装中在衬底晶片或覆盖晶片上采用一个或多个集成氢吸气剂。氢吸气剂设置在衬底晶片或覆盖晶片上的集成电路之间和之间，并且在集成电路制造过程期间被沉积。在一个非限制性实施例中，衬底晶片是III-V族半导体材料，并且吸氢剂包括钛层，镍层和钯层。

6. 发明申请

US20070252643A1 Transistor devices configured to operate above a first cutoff frequency 有权
标题翻译：晶体管器件被配置为在第一截止频率之上操作
公开(公告)号：US20070252643A1
公开(公告)日：2007-11-01
申请号：US11413833
申请日：2006-04-28
申请人： Matt Yuji Nishimoto , Gregory Hoke Rowan , Jeffrey Ming-Jer Yang , Yun-Ho Chung
发明人： Matt Yuji Nishimoto , Gregory Hoke Rowan , Jeffrey Ming-Jer Yang , Yun-Ho Chung
IPC分类号： H03F3/14
CPC分类号： G06F17/5063
摘要： Transistor devices are provided configured to operate at frequencies above a typical first cutoff frequency. In one aspect, a method is provided for configuring a transistor device to operate above a first cutoff frequency. The method comprises selecting a desired operating frequency range and a desired output power for a transistor associated with the transistor device, analyzing the effects of phase velocity mismatch on the overall gain of a plurality of different sized transistors, and evaluating the primary and secondary gain regions of the plurality of different sized transistors. The method further comprises selecting a transistor sized to provide the desired output power at or close to the desired operating frequency range based on the analysis of the phase velocity mismatch and the evaluation of the primary and secondary gain regions.
摘要翻译：晶体管器件被配置为在高于典型的第一截止频率的频率下工作。一方面，提供一种用于配置晶体管器件以在第一截止频率之上操作的方法。该方法包括为与晶体管器件相关联的晶体管选择期望的工作频率范围和期望的输出功率，分析相位速度失配对多个不同尺寸晶体管的总体增益的影响，以及评估初级和次级增益区域的多个不同尺寸的晶体管。该方法还包括选择晶体管，其大小基于对相位速度失配和初级和次级增益区域的评估的分析，在等于或接近期望的工作频率范围提供期望的输出功率。

7. 发明授权

US07239852B2 Asymmetric, optimized common-source bi-directional amplifier 有权
标题翻译：不对称，优化的公共源双向放大器
公开(公告)号：US07239852B2
公开(公告)日：2007-07-03
申请号：US10632683
申请日：2003-08-01
申请人： Jeffrey Ming-Jer Yang , Matt Nishimoto , Yun-Ho Chung , Michael Battung , Richard Lai
发明人： Jeffrey Ming-Jer Yang , Matt Nishimoto , Yun-Ho Chung , Michael Battung , Richard Lai
IPC分类号： H04B1/44
CPC分类号： H03F1/56 , H03F3/193 , H03F3/62 , H03F2200/222 , H03F2200/372 , H03F2200/387 , H03F2200/451 , H04B1/44
摘要： A common source, bi-directional microwave amplifier is described. More particularly, the present invention is a microwave, common source, bi-directional amplifier that includes a first amplification path and a second amplification path wherein the signal directional flow is controlled through the selective biasing of the first amplification path and the second amplification path. Each amplification path is designed to optimize desired performance. For signal flow through the first amplification path, the first amplification path is biased-on and the second path is biased-off. For signal flow through the second amplification path, the second amplification path is biased-on and the first path is biased-off.
摘要翻译：描述了一种常见的源双向微波放大器。更具体地，本发明是一种微波公共源双向放大器，其包括第一放大路径和第二放大路径，其中通过第一放大路径和第二放大路径的选择性偏置来控制信号定向流。每个放大路径被设计为优化所需的性能。对于通过第一放大路径的信号流，第一放大路径被偏置，并且第二路径被偏置。对于通过第二放大路径的信号流，第二放大路径被偏置，并且第一路径被偏置。

8. 发明授权

US06944437B2 Electronically programmable multimode circuit 有权
标题翻译：电子可编程多模电路
公开(公告)号：US06944437B2
公开(公告)日：2005-09-13
申请号：US10705252
申请日：2003-11-10
申请人： Jeffrey Ming-Jer Yang , Matt Nishimoto , Xing Lan , Michael Battung , Robert Wang , Yun-Ho Chung
发明人： Jeffrey Ming-Jer Yang , Matt Nishimoto , Xing Lan , Michael Battung , Robert Wang , Yun-Ho Chung
IPC分类号： H03C3/40 , H03F1/02 , H03F3/21 , H03F3/72 , H04B1/30
CPC分类号： H03F3/72 , H03C3/40 , H03F1/0277 , H03F3/211 , H03F2200/372
摘要： An electronically programmable multimode circuit is described. More particularly, the present invention is an electronically programmable multimode circuit that includes a first path and a second path wherein a mode and a signal directional flow direction is controlled through the selective biasing of the first path and the second path. A multimode circuit is produced that contains modes such as a phase shifter mode, an IQ modulation mode, an amplifier mode, a mixer mode, and a multiplier mode.
摘要翻译：描述了一种电子可编程多模电路。更具体地，本发明是一种电子可编程多模电路，其包括第一路径和第二路径，其中通过第一路径和第二路径的选择性偏置来控制模式和信号方向流动方向。产生包含移相器模式，IQ调制模式，放大器模式，混频器模式和乘法器模式的模式的多模电路。

9. 发明授权

US07498872B2 Transistor devices configured to operate above a first cutoff frequency 有权
标题翻译：晶体管器件被配置为在第一截止频率之上操作
公开(公告)号：US07498872B2
公开(公告)日：2009-03-03
申请号：US11413833
申请日：2006-04-28
申请人： Matt Yuji Nishimoto , Gregory Hoke Rowan , Jeffrey Ming-Jer Yang , Yun-Ho Chung
发明人： Matt Yuji Nishimoto , Gregory Hoke Rowan , Jeffrey Ming-Jer Yang , Yun-Ho Chung
IPC分类号： H01L29/00
CPC分类号： G06F17/5063
摘要： Transistor devices are provided configured to operate at frequencies above a typical first cutoff frequency. In one aspect, a method is provided for configuring a transistor device to operate above a first cutoff frequency. The method comprises selecting a desired operating frequency range and a desired output power for a transistor associated with the transistor device, analyzing the effects of phase velocity mismatch on the overall gain of a plurality of different sized transistors, and evaluating the primary and secondary gain regions of the plurality of different sized transistors. The method further comprises selecting a transistor sized to provide the desired output power at or close to the desired operating frequency range based on the analysis of the phase velocity mismatch and the evaluation of the primary and secondary gain regions.
摘要翻译：晶体管器件被配置为在高于典型的第一截止频率的频率下工作。一方面，提供一种用于配置晶体管器件以在第一截止频率之上操作的方法。该方法包括为与晶体管器件相关联的晶体管选择期望的工作频率范围和期望的输出功率，分析相位速度失配对多个不同尺寸晶体管的总体增益的影响，以及评估初级和次级增益区域的多个不同尺寸的晶体管。该方法还包括选择晶体管，其大小基于对相位速度失配和初级和次级增益区域的评估的分析，在等于或接近期望的工作频率范围提供期望的输出功率。

10. 发明申请

US20090026598A1 Wafer Level Packaging Integrated Hydrogen Getter 有权
标题翻译：晶圆级封装集成式吸氢剂
公开(公告)号：US20090026598A1
公开(公告)日：2009-01-29
申请号：US11782460
申请日：2007-07-24
申请人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
发明人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
IPC分类号： H01L23/26 , H01L21/00
CPC分类号： H01L23/26 , H01L23/053 , H01L23/10 , H01L2924/0002 , H01L2924/1423 , H01L2924/00
摘要： A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.
摘要翻译：晶片级封装，其在晶片级封装中在衬底晶片或覆盖晶片上采用一个或多个集成氢吸气剂。氢吸气剂设置在衬底晶片或覆盖晶片上的集成电路之间和之间，并且在集成电路制造过程期间被沉积。在一个非限制性实施例中，衬底晶片是III-V族半导体材料，并且吸氢剂包括钛层，镍层和钯层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式