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1. 发明申请

US20090026598A1 Wafer Level Packaging Integrated Hydrogen Getter 有权
标题翻译：晶圆级封装集成式吸氢剂
公开(公告)号：US20090026598A1
公开(公告)日：2009-01-29
申请号：US11782460
申请日：2007-07-24
申请人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
发明人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
IPC分类号： H01L23/26 , H01L21/00
CPC分类号： H01L23/26 , H01L23/053 , H01L23/10 , H01L2924/0002 , H01L2924/1423 , H01L2924/00
摘要： A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.
摘要翻译：晶片级封装，其在晶片级封装中在衬底晶片或覆盖晶片上采用一个或多个集成氢吸气剂。氢吸气剂设置在衬底晶片或覆盖晶片上的集成电路之间和之间，并且在集成电路制造过程期间被沉积。在一个非限制性实施例中，衬底晶片是III-V族半导体材料，并且吸氢剂包括钛层，镍层和钯层。

2. 发明授权

US07777318B2 Wafer level packaging integrated hydrogen getter 有权
标题翻译：晶圆级封装集成吸气剂
公开(公告)号：US07777318B2
公开(公告)日：2010-08-17
申请号：US11782460
申请日：2007-07-24
申请人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
发明人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
IPC分类号： H01L23/20
CPC分类号： H01L23/26 , H01L23/053 , H01L23/10 , H01L2924/0002 , H01L2924/1423 , H01L2924/00
摘要： A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.
摘要翻译：晶片级封装，其在晶片级封装中在衬底晶片或覆盖晶片上采用一个或多个集成氢吸气剂。氢吸气剂设置在衬底晶片或覆盖晶片上的集成电路之间和之间，并且在集成电路制造过程期间被沉积。在一个非限制性实施例中，衬底晶片是III-V族半导体材料，并且吸氢剂包括钛层，镍层和钯层。

3. 发明授权

US07696062B2 Method of batch integration of low dielectric substrates with MMICs 有权
标题翻译：低电介质衬底与MMIC的批量集成方法
公开(公告)号：US07696062B2
公开(公告)日：2010-04-13
申请号：US11828147
申请日：2007-07-25
申请人： Patty Pei-Ling Chang-Chien , Chi Kong Cheung , Melanie Sachiko Yajima , Xianglin Zeng
发明人： Patty Pei-Ling Chang-Chien , Chi Kong Cheung , Melanie Sachiko Yajima , Xianglin Zeng
IPC分类号： H01L21/30
CPC分类号： H01L23/66 , H01L21/6835 , H01L21/6836 , H01L25/16 , H01L2221/68327 , H01L2223/6677 , H01L2224/16145 , H01L2224/94 , H01L2924/0002 , H01L2924/1423 , H01Q1/38 , H01L2924/00 , H01L2224/81
摘要： A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.
摘要翻译：将电介质基板安装到半导体基板上的方法，例如将电介质天线基板安装到MMIC半导体基板上。该方法包括提供在相对侧上具有金属化层的薄介电天线基板。在一个实施例中，当金属化层被图案化时，载体晶片用于处理和维持电介质基板处于平坦配置。使用低温接合工艺将电介质基板密封到半导体基板。在替代实施例中，电介质基板上的金属化层被同时图案化，以防止基板卷曲。

4. 发明申请

US20090029554A1 Method of Batch Integration of Low Dielectric Substrates with MMICs 有权
标题翻译：低介电基板与MMIC的批量集成方法
公开(公告)号：US20090029554A1
公开(公告)日：2009-01-29
申请号：US11828147
申请日：2007-07-25
申请人： Patty Pei-Ling Chang-Chien , Chi Kong Cheung , Melanie Sachiko Yajima , Xianglin Zeng
发明人： Patty Pei-Ling Chang-Chien , Chi Kong Cheung , Melanie Sachiko Yajima , Xianglin Zeng
IPC分类号： H01L21/00
CPC分类号： H01L23/66 , H01L21/6835 , H01L21/6836 , H01L25/16 , H01L2221/68327 , H01L2223/6677 , H01L2224/16145 , H01L2224/94 , H01L2924/0002 , H01L2924/1423 , H01Q1/38 , H01L2924/00 , H01L2224/81
摘要： A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.
摘要翻译：将电介质基板安装到半导体基板上的方法，例如将电介质天线基板安装到MMIC半导体基板上。该方法包括提供在相对侧上具有金属化层的薄介电天线基板。在一个实施例中，当金属化层被图案化时，载体晶片用于处理和维持电介质基板处于平坦配置。使用低温接合工艺将电介质基板密封到半导体基板。在替代实施例中，电介质基板上的金属化层被同时图案化，以防止基板卷曲。

5. 发明申请

US20090026619A1 Method for Backside Metallization for Semiconductor Substrate 审中-公开
标题翻译：半导体衬底的背面金属化方法
公开(公告)号：US20090026619A1
公开(公告)日：2009-01-29
申请号：US11782503
申请日：2007-07-24
申请人： Xianglin Zeng , Patty Chang-Chien
发明人： Xianglin Zeng , Patty Chang-Chien
IPC分类号： H01L23/48
CPC分类号： H01L23/585 , H01L23/055 , H01L2924/0002 , H01L2924/01079 , H01L2924/1423 , H01L2924/00
摘要： A wafer circuit, such as a wafer-level package, that includes a semiconductor substrate on which is fabricated one or more integrated circuits. A backside metal layer is deposited on the semiconductor substrate, and is electrically coupled to the integrated circuit by metallized vias extending through the substrate wafer. The backside metal layer is cut to provide electrically isolated backside metal layers for RF, DC and/or ground signals. An adhesion layer is deposited on the backside of the substrate before the metal layer is deposited so that the metal layer is firmly secured to the substrate, and resists peeling. The adhesion layer can be sputtered silicon, sputtered silicon nitride, silicon nitride deposited by chemical vapor deposition, nickel deposited by evaporation and nickel chromium deposited by evaporation.
摘要翻译：诸如晶片级封装的晶片电路，其包括其上制造有一个或多个集成电路的半导体衬底。背面金属层沉积在半导体衬底上，并且通过延伸穿过衬底晶片的金属化通孔电耦合到集成电路。切割背面金属层以提供用于RF，DC和/或接地信号的电隔离的背侧金属层。在沉积金属层之前，在基板的背面上沉积粘合层，使得金属层牢固地固定到基板上，并且抵抗剥离。粘附层可以是溅射硅，溅射氮化硅，通过化学气相沉积沉积的氮化硅，通过蒸发沉积的镍和通过蒸发沉积的镍铬。

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