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1. 发明申请

US20090045437A1 METHOD AND APPARATUS FOR FORMING A SEMI-INSULATING TRANSITION INTERFACE 审中-公开
标题翻译：用于形成半绝缘过渡界面的方法和装置
公开(公告)号：US20090045437A1
公开(公告)日：2009-02-19
申请号：US11839488
申请日：2007-08-15
申请人： Rajinder Sandhu , Abdullah Cavus , Cedric Monier , Augusto Gutierrez
发明人： Rajinder Sandhu , Abdullah Cavus , Cedric Monier , Augusto Gutierrez
IPC分类号： H01L21/20 , H01L31/00
CPC分类号： H01L29/205 , H01L21/02392 , H01L21/02463 , H01L21/02502 , H01L21/02505 , H01L21/0251 , H01L21/02546 , H01L31/184 , H01L31/1844 , Y02E10/544
摘要： The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a first level to a second level; (b) annealing at least the first graded InAlAs layer; (c) depositing the second graded InAlAs layer on the first graded InAlAs layer at the first constant temperature, the second graded InAlAs layer having an In/Al composition ratio which increases across the buffer layer from the second level to a third level; and (d) annealing at least the second graded InAlAs layer; the buffer layer being formed under Groups III/V overpressure.
摘要翻译：本发明涉及形成中间晶格过渡缓冲层的方法。所述方法包括：（a）在第一恒定温度下在衬底上沉积第一渐变InAlAs层，所述第一渐变InAlAs层具有在缓冲层上从第一电平增加到第二电平的In / AI组成比; （b）至少退火第一级分的InAlAs层; （c）在所述第一恒定温度下将所述第二渐变InAlAs层沉积在所述第一梯度InAlAs层上，所述第二渐变InAlAs层具有在所述缓冲层上从所述第二级增加到第三级的In / Al组成比; 和（d）至少退火第二分级的InAlAs层; 该缓冲层在III / V族过压下形成。

2. 发明申请

US20050184312A1 Double HBT base metal micro-bridge 审中-公开
标题翻译：双HBT贱金属微桥
公开(公告)号：US20050184312A1
公开(公告)日：2005-08-25
申请号：US11116745
申请日：2005-04-28
申请人： Donald Sawdai , Gregory Leslie , Augusto Gutierrez-Aitken
发明人： Donald Sawdai , Gregory Leslie , Augusto Gutierrez-Aitken
IPC分类号： H01L29/417 , H01L21/331 , H01L29/423 , H01L29/737 , H01L29/739
CPC分类号： H01L29/66318 , H01L29/42304 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.
摘要翻译：提供了一种有助于降低基极 - 集电极电容的异质结双极晶体管（HBT）器件结构及其制造方法。通过制造将基极接触件连接到HBT上的基底台面的基极微型桥接器来降低基极集电极电容。基极微桥沿着001,1010,00（超晶核（1和0）（超晶圆（10个方向）到晶片的主平面）中的一个取向，HBT器件采用基于磷的收集器材料。磷基集电体材料，基层底切成形微桥，由于微桥的取向，成功地除去桥下的集电体和次集电体材料，集电体和次集电体材料的去除减少了基极 - 集电极结面积，因此降低了基极 - 集电极结电容。

3. 发明授权

US06566724B1 Low dark current photodiode 有权
标题翻译：低暗电流光电二极管
公开(公告)号：US06566724B1
公开(公告)日：2003-05-20
申请号：US09742917
申请日：2000-12-19
申请人： Augusto Gutierrez-Aitken , Edward A. Rezek
发明人： Augusto Gutierrez-Aitken , Edward A. Rezek
IPC分类号： H01L3300
CPC分类号： H01L31/03046 , H01L31/101 , Y02B10/10 , Y02E10/544
摘要： A low dark current photodiode and a method for reducing dark current in a photodiode. A preferred embodiment of the present invention provides a photodiode comprising a barrier layer. The barrier layer comprises a barrier layer material having a wider band-gap than the band-gap of the absorption layer material of the photodiode. The barrier layer comprises sublayers, which are doped to position the high-electric field region at the pn junction of the photodiode in the barrier layer. The method for reducing dark current in a photodiode comprises building a barrier layer into the structure of a photodiode. Building the barrier layer comprises building a layer of semiconductor material with wider band-gap than the i-layer material. Building the barrier layer preferably further comprises doping the barrier layer material to position the high-energy region at the pn junction of the photodiode in the barrier layer, thus reducing dark current.
摘要翻译：低暗电流光电二极管和减少光电二极管中的暗电流的方法。本发明的优选实施例提供一种包括阻挡层的光电二极管。阻挡层包括具有比光电二极管的吸收层材料的带隙更宽的带隙的阻挡层材料。阻挡层包括子层，其被掺杂以将阻挡层中的光电二极管的pn结处的高电场区域定位。用于减少光电二极管中的暗电流的方法包括将阻挡层构建到光电二极管的结构中。构建阻挡层包括构建具有比i层材料更宽的带隙的半导体材料层。构建阻挡层优选还包括掺杂阻挡层材料以将阻挡层中的光电二极管的pn结处的高能区域定位，从而降低暗电流。

4. 发明申请

US20070215280A1 Semiconductor surface processing 审中-公开
标题翻译：半导体表面处理
公开(公告)号：US20070215280A1
公开(公告)日：2007-09-20
申请号：US11375717
申请日：2006-03-15
申请人： Rajinder Sandhu , Roosevelt Johnson , Cedric Monier , Augusto Gutierrez-Aitken
发明人： Rajinder Sandhu , Roosevelt Johnson , Cedric Monier , Augusto Gutierrez-Aitken
IPC分类号： C03C15/00 , H01L21/306 , H01L21/302
CPC分类号： H01L21/02024 , B24B37/042 , B24B57/02
摘要： A semiconductor surface processing method in one example comprises disposing a polishing pad in rotating engagement with a semiconductor wafer to be polished, dripping a first polishing solution onto the polishing pad at a first drip rate, and, concurrently, dripping a second polishing solution onto the polishing pad at a second drip rate.
摘要翻译：在一个实例中的半导体表面处理方法包括：将抛光垫设置成与要抛光的半导体晶片旋转接合，以第一滴落速率将第一抛光溶液滴到抛光垫上，并且同时将第二抛光溶液滴到抛光垫以第二滴液速率。

5. 发明授权

US06924203B2 Double HBT base metal micro-bridge 有权
公开(公告)号：US06924203B2
公开(公告)日：2005-08-02
申请号：US10445612
申请日：2003-05-27
申请人： Donald James Sawdai , Gregory Scott Leslie , Augusto Gutierrez-Aitken
发明人： Donald James Sawdai , Gregory Scott Leslie , Augusto Gutierrez-Aitken
IPC分类号： H01L29/417 , H01L21/331 , H01L29/423 , H01L29/737 , H01L21/332
CPC分类号： H01L29/66318 , H01L29/42304 , H01L29/7371
摘要： A heterojunction bipolar transistor (HBT) device structure is provided which facilitates the reduction of the base-collector capacitance and a method for making the same. The base-collector capacitance is decreased by fabricating a base micro-bridge connecting a base contact to a base mesa on the HBT. The base micro-bridge is oriented along about one of 001, 010, 00{overscore (1)}, and 0{overscore (1)}0 direction to a major flat of the wafer. The HBT device employs a phosphorous based collector material. During removal of the phosphorous based collector material, the base layer is undercut forming the micro-bridge, successfully removing the collector and sub-collector material below the bridge due to the orientation of the micro-bridge. The removal of collector and sub-collector material reduces the base-collector junction area, and therefore reduce the base-collector junction capacitance.

6. 发明申请

US20090065811A1 Semiconductor Device with OHMIC Contact and Method of Making the Same 审中-公开
标题翻译：具有OHMIC触点的半导体器件及其制造方法
公开(公告)号：US20090065811A1
公开(公告)日：2009-03-12
申请号：US11851968
申请日：2007-09-07
申请人： Ping-Chih Chang , Xiaobing Mei , Augusto Gutierrez-Aitken
发明人： Ping-Chih Chang , Xiaobing Mei , Augusto Gutierrez-Aitken
IPC分类号： H01L29/737 , H01L21/3205
CPC分类号： H01L29/7371 , H01L29/205 , H01L29/452
摘要： A semiconductor device with ohmic contact is provided with a method of making the same. In one embodiment, a method is provided for fabricating a semiconductor device. The method comprises providing a semiconductor structure with a N-type doped semiconductor contact layer, forming a platinum contact portion over the N-type doped semiconductor contact layer, forming an adhesive contact portion over the platinum contact portion, forming a barrier contact portion over the adhesive contact portion, and forming a gold contact portion over the barrier contact portion. The method further comprises annealing the semiconductor structure to alloy the platinum contact portion with the N-type doped semiconductor contact layer to form a platinum/semiconductor alloyed diffusion contact barrier substantially disposed within the N-type doped semiconductor contact layer.
摘要翻译：具有欧姆接触的半导体器件具有制造其的方法。在一个实施例中，提供了一种用于制造半导体器件的方法。该方法包括提供具有N型掺杂半导体接触层的半导体结构，在N型掺杂半导体接触层上形成铂接触部分，在铂接触部分上方形成粘合剂接触部分，粘合剂接触部分，并且在阻挡接触部分上形成金接触部分。该方法还包括退火半导体结构以将铂接触部分与N型掺杂半导体接触层合金，以形成基本上设置在N型掺杂半导体接触层内的铂/半导体合金扩散接触屏障。

7. 发明申请

US20080251891A1 Semiconductor having passivated sidewalls 审中-公开
标题翻译：具有钝化侧壁的半导体
公开(公告)号：US20080251891A1
公开(公告)日：2008-10-16
申请号：US11784872
申请日：2007-04-10
申请人： Yeong-Chang Chou , Peter S. Nam , Chun H. Lin , Augusto Gutierrez , Jeffrey Ming-Jer Yang , Michael Wojtowicz
发明人： Yeong-Chang Chou , Peter S. Nam , Chun H. Lin , Augusto Gutierrez , Jeffrey Ming-Jer Yang , Michael Wojtowicz
IPC分类号： H01L23/58 , H01L21/00
CPC分类号： H01L21/31612 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/3145
摘要： The layers of a semiconductor device have exposed edges. The layers that are susceptible to oxidation are protected from oxidation by coating them with a nitride passivation layer. The nitride passivation layer can be applied using plasma enhanced chemical vapor deposition (PECVD). A method of making a passivated sidewall semiconductor includes the steps of applying a nitride or other protective material over a wafer using PECVD or other appropriate deposition method.
摘要翻译：半导体器件的层具有暴露边缘。易受氧化的层通过用氮化物钝化层涂覆而防止氧化。可以使用等离子体增强化学气相沉积（PECVD）来施加氮化物钝化层。制造钝化侧壁半导体的方法包括以下步骤：使用PECVD或其它合适的沉积方法在晶片上施加氮化物或其它保护材料。

8. 发明申请

US20080230803A1 Integrated Contact Interface Layer 审中-公开
标题翻译：集成接口接口层
公开(公告)号：US20080230803A1
公开(公告)日：2008-09-25
申请号：US11689945
申请日：2007-03-22
申请人： Cedric Monier , Randy Sandhu , Abdullah Cavus , Augusto Gutierrez-Aitken
发明人： Cedric Monier , Randy Sandhu , Abdullah Cavus , Augusto Gutierrez-Aitken
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7371 , H01L29/0821 , H01L29/1004 , H01L29/201 , H01L29/66318
摘要： A semiconductor device that is fabricated by metamorphic epitaxial growth processes, and includes a combined graded base and active layer having a thickness less than 5000 Å. In one non-limiting embodiment, the semiconductor device is an HBT device that includes a combined doped graded buffer and sub-collector layer having a thickness less than 5000 Å, and a concentration of indium of about 86% at a top of the combined layer.
摘要翻译：通过变质外延生长工艺制造的半导体器件，并且包括厚度小于5000的组合的梯度基底和有源层。在一个非限制性实施例中，半导体器件是HBT器件，其包括厚度小于Å的组合掺杂渐变缓冲器和次集电极层，并且在组合层的顶部具有约86％的铟浓度。

9. 发明授权

US5679478A Reserve battery having simplified construction and improved range of operation 失效
标题翻译：储备电池结构简单，操作范围更广
公开(公告)号：US5679478A
公开(公告)日：1997-10-21
申请号：US600552
申请日：1996-02-13
申请人： Keith Alan Hancock , Thomas Augusto Gutierrez , Jeffrey Michael Kalman , Nicholas Emile Stanca
发明人： Keith Alan Hancock , Thomas Augusto Gutierrez , Jeffrey Michael Kalman , Nicholas Emile Stanca
IPC分类号： H01M6/38 , H01M6/42 , H01M10/06 , H01M10/50 , H01M6/32
CPC分类号： H01M10/06 , H01M10/615 , H01M10/654 , H01M10/6595 , H01M6/38 , H01M6/42
摘要： A reserve, energy sourced, or deferred action battery in which each battery cell is provided a separate reservoir containing the necessary electrolyte fluid for that cell. A simple design is then possible as the electrolyte fluid is stored in close proximity to the battery cells when needed at the time of activating the battery. A combination of two electrolyte fluids may be used that react exothermically when mixed together at the time of activation thereby producing heat. The production of heat allows the battery to activate at existing cold ambient temperatures that would otherwise render the reserve battery without sufficient operating power. The invention also provides an activation system which ensures reliable activation of the battery and ensures that the battery is not is subject to unintended activation.
摘要翻译：储备，能量源或延迟动作电池，其中每个电池单元被提供有单独的储存器，其容纳该电池所需的电解液。因此，当活化电池时需要电解质流体被储存在电池单元附近时，可以进行简单的设计。可以使用在活化时混合在一起而产生热量时放热反应的两种电解质流体的组合。热量的产生允许电池在现有的冷环境温度下激活，否则将导致储备电池没有足够的操作功率。本发明还提供一种激活系统，其确保电池的可靠启动并确保电池不被无意地激活。

10. 发明授权

US5668461A Reserve battery having temperture compensation 失效
标题翻译：保留电池有温度补偿
公开(公告)号：US5668461A
公开(公告)日：1997-09-16
申请号：US600551
申请日：1996-02-13
申请人： Keith Alan Hancock , Joseph Thomas Scopaz , Gerald Lewis , Thomas Augusto Gutierrez
发明人： Keith Alan Hancock , Joseph Thomas Scopaz , Gerald Lewis , Thomas Augusto Gutierrez
IPC分类号： B60R16/02 , B60R16/03 , H02J7/00 , H01M10/46
CPC分类号： H02J7/0054 , H02J7/0034 , B60R16/03
摘要： An electronic control system for a reserve, energy sourced, or deferred action battery that determines start-up temperature and voltage conditions to determine the necessary amount of charge to deliver from a reserve battery to a discharged battery. A temperature sensor is used to measure the ambient temperature and operating temperature of the electronic control system. A target charge value is selected based on the ambient temperature and startup voltage information. The operating temperature of the electronics control system is monitored to ensure the most efficient and reliable delivery of charge. Indications are provided to the user to provide information regarding charging status, connection status, and voltage levels.
摘要翻译：一种用于储备，能量源或延迟动作电池的电子控制系统，其确定启动温度和电压条件，以确定从备用电池传送到放电电池的必要的充电量。温度传感器用于测量电子控制系统的环境温度和工作温度。基于环境温度和启动电压信息选择目标电荷值。对电子控制系统的工作温度进行监控，以确保最高效，可靠的运输。向用户提供指示以提供关于充电状态，连接状态和电压电平的信息。

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