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    • 5. 发明授权
    • Transistor devices configured to operate above a first cutoff frequency
    • 晶体管器件被配置为在第一截止频率之上操作
    • US07498872B2
    • 2009-03-03
    • US11413833
    • 2006-04-28
    • Matt Yuji NishimotoGregory Hoke RowanJeffrey Ming-Jer YangYun-Ho Chung
    • Matt Yuji NishimotoGregory Hoke RowanJeffrey Ming-Jer YangYun-Ho Chung
    • H01L29/00
    • G06F17/5063
    • Transistor devices are provided configured to operate at frequencies above a typical first cutoff frequency. In one aspect, a method is provided for configuring a transistor device to operate above a first cutoff frequency. The method comprises selecting a desired operating frequency range and a desired output power for a transistor associated with the transistor device, analyzing the effects of phase velocity mismatch on the overall gain of a plurality of different sized transistors, and evaluating the primary and secondary gain regions of the plurality of different sized transistors. The method further comprises selecting a transistor sized to provide the desired output power at or close to the desired operating frequency range based on the analysis of the phase velocity mismatch and the evaluation of the primary and secondary gain regions.
    • 晶体管器件被配置为在高于典型的第一截止频率的频率下工作。 一方面,提供一种用于配置晶体管器件以在第一截止频率之上操作的方法。 该方法包括为与晶体管器件相关联的晶体管选择期望的工作频率范围和期望的输出功率,分析相位速度失配对多个不同尺寸晶体管的总体增益的影响,以及评估初级和次级增益区域 的多个不同尺寸的晶体管。 该方法还包括选择晶体管,其大小基于对相位速度失配和初级和次级增益区域的评估的分析,在等于或接近期望的工作频率范围提供期望的输出功率。
    • 7. 发明申请
    • Transistor devices configured to operate above a first cutoff frequency
    • 晶体管器件被配置为在第一截止频率之上操作
    • US20070252643A1
    • 2007-11-01
    • US11413833
    • 2006-04-28
    • Matt Yuji NishimotoGregory Hoke RowanJeffrey Ming-Jer YangYun-Ho Chung
    • Matt Yuji NishimotoGregory Hoke RowanJeffrey Ming-Jer YangYun-Ho Chung
    • H03F3/14
    • G06F17/5063
    • Transistor devices are provided configured to operate at frequencies above a typical first cutoff frequency. In one aspect, a method is provided for configuring a transistor device to operate above a first cutoff frequency. The method comprises selecting a desired operating frequency range and a desired output power for a transistor associated with the transistor device, analyzing the effects of phase velocity mismatch on the overall gain of a plurality of different sized transistors, and evaluating the primary and secondary gain regions of the plurality of different sized transistors. The method further comprises selecting a transistor sized to provide the desired output power at or close to the desired operating frequency range based on the analysis of the phase velocity mismatch and the evaluation of the primary and secondary gain regions.
    • 晶体管器件被配置为在高于典型的第一截止频率的频率下工作。 一方面,提供一种用于配置晶体管器件以在第一截止频率之上操作的方法。 该方法包括为与晶体管器件相关联的晶体管选择期望的工作频率范围和期望的输出功率,分析相位速度失配对多个不同尺寸晶体管的总体增益的影响,以及评估初级和次级增益区域 的多个不同尺寸的晶体管。 该方法还包括选择晶体管,其大小基于对相位速度失配和初级和次级增益区域的评估的分析,在等于或接近期望的工作频率范围提供期望的输出功率。
    • 10. 发明授权
    • Asymmetric, voltage optimized, wideband common-gate bi-directional MMIC amplifier
    • 不对称,电压优化,宽带共栅双向MMIC放大器
    • US06657497B1
    • 2003-12-02
    • US10160140
    • 2002-05-30
    • Jeffrey M. YangYun-Ho ChungMatt Y. Nishimoto
    • Jeffrey M. YangYun-Ho ChungMatt Y. Nishimoto
    • H03F316
    • H03F3/607H03F1/08H03F1/56H03F3/62H03F2200/294H03F2200/372H03F2200/72
    • A bi-directional amplifier (10) for a transceiver module for amplifying both transmit signals and receive signals propagating in opposite directions. The amplifier (10) includes first and second common gate FETs (22, 24) electrically coupled along a common transmission line (20). A first variable matching network (28) is electrically coupled to the transmission line (20) between a transmit signal input port (12) and the first FET (22), and a second variable matching network (30) is electrically coupled to the transmission line (20) between a receive signal input port (14) and the second FET (24). An interstage variable matching network (32) is electrically coupled to the transmission line (20) between the first and second FETs (22, 24). A DC voltage regulator (34) provides a DC bias signal to the matching networks (28, 30, 32) and the FETs (22, 24) so that different signal amplifications and different impedance matching characteristics can be provided for the transmit signal and the receive signal.
    • 一种用于收发器模块的双向放大器(10),用于放大发送信号和接收在相反方向上传播的信号。 放大器(10)包括沿着公共传输线(20)电耦合的第一和第二公共栅极FET(22,24)。 第一可变匹配网络(28)电耦合到发射信号输入端口(12)和第一FET(22)之间的传输线(20),并且第二可变匹配网络(30)电耦合到传输 在接收信号输入端口(14)和第二FET(24)之间的线路(20)。 级间变量匹配网络(32)电耦合到第一和第二FET(22,24)之间的传输线(20)。 直流电压调节器(34)向匹配网络(28,30,32)和FET(22,24)提供DC偏置信号,使得可以为发射信号提供不同的信号放大和不同的阻抗匹配特性, 接收信号。