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1. 发明授权

US3930947A Method of producing microbial cells from methane 失效
标题翻译：从甲烷生产微生物细胞的方法
公开(公告)号：US3930947A
公开(公告)日：1976-01-06
申请号：US534144
申请日：1974-12-18
申请人： Yasushi Morinaga , Shigeru Yamanaka , Yoshio Hirose
发明人： Yasushi Morinaga , Shigeru Yamanaka , Yoshio Hirose
IPC分类号： C12N1/00 , A23K1/16 , C12N1/20 , C12N1/26 , C12N1/30 , C12B1/00
CPC分类号： C12N1/30 , Y10S435/822
摘要： A novel strain belonging to genus Methylomonas grows well on a culture medium in the presence of methane as the main carbon source. The microbial cells are useful as a feedstuff.

2. 发明授权

US07349998B2 Bus control system for integrated circuit device with improved bus access efficiency 有权
标题翻译：集成电路设备总线控制系统，提高总线访问效率
公开(公告)号：US07349998B2
公开(公告)日：2008-03-25
申请号：US11136417
申请日：2005-05-25
申请人： Yoshio Hirose , Hiroyuki Utsumi , Toshiaki Saruwatari
发明人： Yoshio Hirose , Hiroyuki Utsumi , Toshiaki Saruwatari
IPC分类号： G06F3/00
CPC分类号： G06F13/126 , G06F9/3879
摘要： The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIs) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.
摘要翻译：本发明是在LSI发出命令或数据（发行侧LSI）的两个集成电路装置（以下称为LSI）之间的命令或数据传送，其将指示有效的命令或数据被发送的选通信号输出到LSI 其接收命令或数据（接收侧LSI），并且接收侧LSI将通知命令处理完成的信号（命令就绪信号）输出到发行侧LSI。发行方LSI包括计数器，其中指示接收侧LSI可以同时处理或同时接收的命令数的值在初始化时被加载，其中当发出命令或数据时计数器递减，当计数器递增时，计数器递增接收就绪信号，并且当计数器变为“0”时禁止发出命令或数据。因此，发行方LSI可以向接收侧LSI发出命令或数据，而不确认来自接收侧LSI的忙信号。

3. 发明授权

US07114061B2 Information processing apparatus with configurable processor 有权
标题翻译：具有可配置处理器的信息处理设备
公开(公告)号：US07114061B2
公开(公告)日：2006-09-26
申请号：US10627709
申请日：2003-07-28
申请人： Yoshio Hirose , Miyoshi Saito , Wouter Couzijn
发明人： Yoshio Hirose , Miyoshi Saito , Wouter Couzijn
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F9/3885 , G06F9/3897 , G06F17/5045
摘要： In a processor, an operating unit executes an instruction within an instruction set, and a second operating unit executes other custom instructions. The second operating unit consists of a plurality of AND circuits, OR circuits, adders, selectors, and multiplexers. The information about which circuit should be combined with which circuit when the instruction is input is held in advance as structure information in a configuration memory. One piece of structure information corresponds to one custom instruction. The second operating unit in an optimum circuit structure determined based on this structure information executes the instruction. With this arrangement, it is possible to increase the processing speed than when the operating unit executes the processing.
摘要翻译：在处理器中，操作单元执行指令集内的指令，第二操作单元执行其他定制指令。第二操作单元由多个AND电路，OR电路，加法器，选择器和多路复用器组成。在配置存储器中作为结构信息预先保存关于哪个电路与输入指令时的电路组合的信息。一条结构信息对应于一条定制指令。基于该结构信息确定的最佳电路结构中的第二操作单元执行该指令。通过这种布置，与操作单元执行处理相比，可以提高处理速度。

4. 外观设计

USD370894S Disc drive 失效
公开(公告)号：USD370894S
公开(公告)日：1996-06-18
申请号：US665452
申请日：1991-03-06
申请人： Yoshio Hirose
设计人： Yoshio Hirose

5. 发明授权

US5283702A Power saving system for rotating disk data storage apparatus 失效
标题翻译：旋转磁盘数据存储装置的节电系统
公开(公告)号：US5283702A
公开(公告)日：1994-02-01
申请号：US746773
申请日：1991-08-16
申请人： Hiroshi Tsuyuguchi , Yoshio Hirose , Kazuhiko Inoue , Tohru Miura , Miya Enami
发明人： Hiroshi Tsuyuguchi , Yoshio Hirose , Kazuhiko Inoue , Tohru Miura , Miya Enami
IPC分类号： G11B5/55 , G11B19/00 , G11B19/20 , G11B21/08 , G11B5/596
CPC分类号： G11B19/20 , G11B19/00 , G11B5/5547
摘要： A flexible magnetic disk drive is disclosed which has a stepper motor coupled to a data transducer via a steel belt motion translating mechanism for moving the transducer from track to track on the rotating disk in response to stepping pulses and a stepping direction signal from an external host system. In order to save power, the stepper motor is held deenergized while the disk drive motor is out of rotation, with the consequent possibility that the transducer may be displaced from the required track position on the disk while the stepper motor is held deenergized. Therefore, in order to always memorize the latest of the successive destination tracks commanded by the host system, a forward/backward counter is provided which counts the external stepping pulses in either direction depending upon the binary state of the external stepping direction signal. After the disk drive motor is set into rotation, stepping pulses and an stepping direction signal are generated internally for causing the stepper motor to automatically reposition the transducer on the memorized latest destination track.
摘要翻译：公开了一种柔性磁盘驱动器，其具有经由钢带运动转换机构耦合到数据传感器的步进电机，用于响应于步进脉冲和来自外部主机的步进方向信号将转换器从轨道移动到旋转盘上系统。为了节省电力，步进电动机在磁盘驱动电动机不能旋转的同时保持断电，从而随着步进电动机被断电而使换能器从盘上所需轨道位置移位的可能性。因此，为了始终存储由主机系统指令的连续的目的地轨迹的最新，提供了前向/后向计数器，其根据外部步进方向信号的二进制状态对任一方向的外部步进脉冲进行计数。在磁盘驱动电动机转动之后，内部产生步进脉冲和步进方向信号，使步进电动机自动地将换能器重新定位在存储的最新目的地轨道上。

6. 发明授权

US4842500A Vane pump with positioning pins for cam ring 失效
标题翻译：叶片泵带有凸轮环定位销
公开(公告)号：US4842500A
公开(公告)日：1989-06-27
申请号：US230701
申请日：1988-08-09
申请人： Tohru Fujie , Yoshio Hirose
发明人： Tohru Fujie , Yoshio Hirose
IPC分类号： F04C2/344 , F01C21/10 , F04C15/00
CPC分类号： F01C21/10 , F04C15/00 , F04C2230/603 , Y10T29/49245
摘要： A vane pump comprising a housing having front and rear surfaces and formed with a cam ring housing portion which is open to the front surface, the housing being further formed at its inner peripheral wall with recess portions and an axial bore extending from the rear surface, said axial bore being open to a center of the ring housing portion; a drive shaft freely rotatably supported in the axial bore of the housing; a rotor inserted on the drive shaft and engaged with the drive shaft, the rotor having a plurality of slits and a plurality of vanes each projectable from and retractable in the corresponding slit; a cam ring having at its inner peripheral wall a cam surface which is arranged to enclose the rotor therein and form pump chambers in cooperation with the vanes, the cam ring being formed at its outer peripheral wall with recess portions of substantially semicircular configuration in cross section; a front end plate by which the cam ring is closed at its one end; a rear end plate formed with a bearing portion through which one end portion of the drive shaft is freely rotatably supported, the rear end plate also formed with at least a pair of openings, each of the openings being spaced at a predetermined distance from a center axis of the bearing portion of the rear end plate; and knock pins fixedly inserted in the openings of the rear end plate, disposed to engage the cam ring in the semicircular recess portions of the cam ring, and disposed with clearance in bores defined by the recess portions of the housing so that the cam ring is held and positioned only with respect to the rear end plate.
摘要翻译：一种叶片泵，包括具有前表面和后表面的壳体，并且形成有朝向前表面开口的凸轮环容纳部分，所述壳体在其内周壁处进一步形成有凹部和从后表面延伸的轴向孔，所述轴向孔向所述环容纳部分的中心开口; 驱动轴，其自由旋转地支撑在壳体的轴向孔中; 转子，其插入在驱动轴上并与驱动轴接合，转子具有多个狭缝和多个叶片，每个叶片能够在相应的狭缝中伸出并缩回; 凸轮环在其内周壁处具有凸轮表面，所述凸轮表面布置成将转子包围在其中并与叶片协作地形成泵室，所述凸轮环在其外周壁处形成有大致半圆形构造的凹部，横截面 ; 前端板，凸轮环在其一端封闭; 后端板，其形成有轴承部分，驱动轴的一个端部通过该轴承部分自由旋转地支撑，后端板还形成有至少一对开口，每个开口与中心隔开预定的距离后端板的轴承部的轴线; 以及固定地插入在后端板的开口中的敲针，其设置成将凸轮环接合在凸轮环的半圆形凹部中，并且间隙设置在由壳体的凹部限定的孔中，使得凸轮环为只能相对于后端板固定和定位。

7. 发明授权

US07096375B2 Data transfer circuit between different clock regions 失效
公开(公告)号：US07096375B2
公开(公告)日：2006-08-22
申请号：US10299063
申请日：2002-11-19
申请人： Shigetoshi Wakayama , Hiroshi Okano , Yoshio Hirose
发明人： Shigetoshi Wakayama , Hiroshi Okano , Yoshio Hirose
IPC分类号： G06F1/12 , G06F5/06 , G06F3/00
CPC分类号： G06F5/06
摘要： A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.

8. 发明授权

US06917995B2 Bus control system for integrated circuit device with improved bus access efficiency 有权
标题翻译：集成电路设备总线控制系统，提高总线访问效率
公开(公告)号：US06917995B2
公开(公告)日：2005-07-12
申请号：US09739835
申请日：2000-12-20
申请人： Yoshio Hirose , Hiroyuki Utsumi , Toshiaki Saruwatari
发明人： Yoshio Hirose , Hiroyuki Utsumi , Toshiaki Saruwatari
IPC分类号： G06F13/36 , G06F9/38 , G06F13/12 , G06F13/28 , G06F13/00
CPC分类号： G06F13/126 , G06F9/3879
摘要： The present invention is a command or data transfer between two integrated circuit devices (hereafter LSIS) wherein an LSI issuing a command or data (issuing side LSI) outputs a strobe signal, which indicates that a valid command or data was transmitted, to the LSI which receives the command or data (receiving side LSI), and the receiving side LSI outputs a signal, which notifies that the command processing completed (command ready signal), to the issuing side LSI. The issuing side LSI comprises a counter where a value to indicate the number of commands which the receiving side LSI can simultaneously process or simultaneously receive is loaded at initialization, wherein the counter is decremented when a command or data is issued, the counter is incremented when the ready signal is received, and issuing a command or data is inhibited when the counter becomes “0”. Therefore the issuing side LSI can issue a command or data to the receiving side LSI without confirming a busy signal from the receiving side LSI.
摘要翻译：本发明是两个集成电路装置（以下称为LSIS）之间的命令或数据传送，其中发出命令或数据（发行方LSI）的LSI将指示有效命令或数据被发送的选通信号输出到LSI 其接收命令或数据（接收侧LSI），并且接收侧LSI将通知命令处理完成的信号（命令就绪信号）输出到发行侧LSI。发行方LSI包括计数器，其中指示接收侧LSI可以同时处理或同时接收的命令数的值在初始化时被加载，其中当发出命令或数据时计数器递减，当计数器递增时，计数器递增接收就绪信号，并且当计数器变为“0”时禁止发出命令或数据。因此，发行方LSI可以向接收侧LSI发出命令或数据，而不确认来自接收侧LSI的忙信号。

9. 发明授权

US06868472B1 Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory 失效
标题翻译：控制和寻址作为随机地址存储器以增加对主存储器的访问速度的高速缓冲存储器的方法
公开(公告)号：US06868472B1
公开(公告)日：2005-03-15
申请号：US09671117
申请日：2000-09-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515
摘要： In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.
摘要翻译：在本发明的高速缓冲存储器控制方法和计算机中，高速缓存存储器连接到主存储器并被分成多个高速缓存块，并且锁定/解锁信号被提供给高速缓冲存储器以设置替换抑制禁止将至少一个高速缓存块替换为主存储器的至少一个缓存块的状态，或者重置至少一个高速缓冲存储器时钟的替换禁止状态，使得更换高速缓存中的至少一个阻塞到主内存是允许的。通过使用高速缓冲存储器的其余高速缓冲存储器（除了至少一个高速缓存块之外）来执行读取或写入主存储器，使得当通过锁定/解锁信号设置替换禁止状态时，在主存储器的读取或写入期间禁止将至少一个缓存块替换到主存储器。

10. 发明授权

US6073249A Information processing system 有权
标题翻译：信息处理系统
公开(公告)号：US6073249A
公开(公告)日：2000-06-06
申请号：US140797
申请日：1998-08-26
申请人： Toru Watabe , Yasutomo Sakurai , Takumi Kishino , Yoshio Hirose , Koichi Odahara , Kazuhiro Nonomura , Takumi Takeno , Shinya Katoh , Takato Noda
发明人： Toru Watabe , Yasutomo Sakurai , Takumi Kishino , Yoshio Hirose , Koichi Odahara , Kazuhiro Nonomura , Takumi Takeno , Shinya Katoh , Takato Noda
IPC分类号： G06F11/00 , G06F11/14 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/22 , G06F13/00
CPC分类号： G06F11/1658 , G06F11/1679 , G06F11/18 , G06F11/182 , G06F11/2041 , G06F11/1402 , G06F11/1675 , G06F11/22
摘要： A TMR unit connects a plurality of processors by a bus and simultaneously executes the same processing operation. Among the plurality of processors, one of them is a master and the remaining processors are slaves. Information formed by only the master processor is outputted to the bus. Each processor has a multiplex control circuit. The multiplex control circuit compares output information formed by itself with bus information outputted to the bus, thereby detecting a failure and allowing an internal circuit to execute necessary processes.
摘要翻译： TMR单元通过总线连接多个处理器，并且同时执行相同的处理操作。在多个处理器中，其中之一是主机，其余的处理器是从机。仅由主处理器形成的信息被输出到总线。每个处理器具有多路复用控制电路。多路复用控制电路将自身形成的输出信息与输出到总线的总线信息进行比较，从而检测故障并允许内部电路执行必要的处理。

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