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1. 发明授权

US07256474B2 Semiconductor device having a guard ring 有权
标题翻译：具有保护环的半导体器件
公开(公告)号：US07256474B2
公开(公告)日：2007-08-14
申请号：US10777189
申请日：2004-02-13
申请人： Shigetoshi Wakayama , Mutsuaki Kai , Hiroyuki Kato , Masato Suga
发明人： Shigetoshi Wakayama , Mutsuaki Kai , Hiroyuki Kato , Masato Suga
IPC分类号： H01L23/544
CPC分类号： H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.
摘要翻译：半导体器件的多层互连结构包括沿着衬底的周边连续延伸的第一保护环和沿着周边在多层互连结构中连续延伸的第二保护环，以便被第一保护环包围，从而围绕所述多层互连结构内部的互连图案，其中所述第一和第二保护环通过桥接导体图案彼此机械连续地连接，所述桥接导体图案沿着包括所述第一和第二保护环的区域以带状连续延伸，垂直于衬底的方向。

2. 发明授权

US07096375B2 Data transfer circuit between different clock regions 失效
公开(公告)号：US07096375B2
公开(公告)日：2006-08-22
申请号：US10299063
申请日：2002-11-19
申请人： Shigetoshi Wakayama , Hiroshi Okano , Yoshio Hirose
发明人： Shigetoshi Wakayama , Hiroshi Okano , Yoshio Hirose
IPC分类号： G06F1/12 , G06F5/06 , G06F3/00
CPC分类号： G06F5/06
摘要： A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.

3. 发明授权

US06205076B1 Destructive read type memory circuit, restoring circuit for the same and sense amplifier 有权
公开(公告)号：US06205076B1
公开(公告)日：2001-03-20
申请号：US09276690
申请日：1999-03-26
申请人： Shigetoshi Wakayama , Kohtaroh Gotoh , Miyoshi Saito , Junji Ogawa
发明人： Shigetoshi Wakayama , Kohtaroh Gotoh , Miyoshi Saito , Junji Ogawa
IPC分类号： G11C700
CPC分类号： G11C7/065 , G11C7/06 , G11C11/4091
摘要： A restoring circuit 24, provided for each of the memory blocks 191 and 192, having registers and a selector for selecting one of the present row address and the output of the registers, provides the output of the selector to a word decoder 26. The present row address is held in one of the registers. When amplification is started by a sense amplifier 15, transfer gates 10 and 11 connected between the bit lines BL1 and *BL1 and the sense amplifier 15 are turned off to decrease the load of the sense amplifier 15, the amplified signal is stored in a buffer memory cell circuit 18, and accessing is completed with omitting restoring to the memory cell 12. While the memory cell block 191 is not selected, the data held in the buffer memory cell circuit 18 is stored into the memory cell row addressed by the content of the selected register. The sense amplifier 15 has PMOS and NMOS sense amplifiers. The PMOS sense amplifier, having a pair of cross-coupled PMOS transistors and a pair of transfer gates, the potential of the sources of the PMOS transistors being fixed at Vii, operates in a direct sensing mode when the transfer gates are off state, and then functions as a usual PMOS sense amplifier by turning on the transfer gates. Likewise for the NMOS sense amplifier.

4. 发明授权

US6157688A Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system 失效
公开(公告)号：US6157688A
公开(公告)日：2000-12-05
申请号：US944516
申请日：1997-10-06
申请人： Hirotaka Tamura , Miyoshi Saito , Kohtaroh Gotoh , Shigetoshi Wakayama , Junji Ogawa , Hisakatsu Araki , Tsz-shing Cheung
发明人： Hirotaka Tamura , Miyoshi Saito , Kohtaroh Gotoh , Shigetoshi Wakayama , Junji Ogawa , Hisakatsu Araki , Tsz-shing Cheung
IPC分类号： G06F3/00 , G06F1/10 , G06F12/00 , G06F13/16 , G06F13/42 , G11C11/401 , G11C11/407 , G11C11/409 , H04B14/06 , G11C16/06
CPC分类号： H04L25/0276 , G06F13/4243 , H04L25/0278 , H04L25/0282 , H04L25/0288 , H04L25/497 , Y02B60/1228 , Y02B60/1235
摘要： A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

5. 发明授权

US6064244A Phase-locked loop circuit permitting reduction of circuit size 失效
标题翻译：锁相环电路允许减小电路尺寸
公开(公告)号：US6064244A
公开(公告)日：2000-05-16
申请号：US813632
申请日：1997-03-07
申请人： Shigetoshi Wakayama , Kohtaroh Gotoh , Miyoshi Saito , Junji Ogawa , Hirotaka Tamura
发明人： Shigetoshi Wakayama , Kohtaroh Gotoh , Miyoshi Saito , Junji Ogawa , Hirotaka Tamura
IPC分类号： H03L7/00 , G06F1/06 , G11C7/22 , G11C11/407 , H03K23/54 , H03K23/66 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/033 , H03L7/06
CPC分类号： H03L7/0997 , G11C7/22 , H03K23/54 , H03K23/548 , H03K23/66 , H03L7/0814 , H03L7/089
摘要： A phase-locked loop circuit is constituted in such a manner that a delayed signal created by causing an input signal to loop through a delay stage a plurality of times is compared in terms of phase with the input signal, and an amount of delay in the delay stage is controlled in accordance with the comparison result of the delayed signal and the input signal. Therefore, the circuit size can be reduced with a reduced number of delay units constituting the delay stage.
摘要翻译：锁相环电路以这样的方式构成，使得通过使输入信号多次循环延迟级而产生的延迟信号在与输入信号的相位方面进行比较，并且在根据延迟信号和输入信号的比较结果控制延迟级。因此，可以减少构成延迟级的延迟单元的数量来减小电路尺寸。

6. 发明授权

US06247138B1 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system 失效
公开(公告)号：US06247138B1
公开(公告)日：2001-06-12
申请号：US09093056
申请日：1998-06-08
申请人： Hirotaka Tamura , Hisakatsu Araki , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Araki , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F104
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

7. 发明授权

US07342434B2 Semiconductor device including capacitor having decoupling capacity 失效
标题翻译：包括具有去耦能力的电容器的半导体器件
公开(公告)号：US07342434B2
公开(公告)日：2008-03-11
申请号：US11042090
申请日：2005-01-26
申请人： Shigetoshi Wakayama , Mutsuaki Kai
发明人： Shigetoshi Wakayama , Mutsuaki Kai
IPC分类号： G11C5/14
CPC分类号： H03F3/45183 , H03F1/52 , H03F1/523 , H03F3/45475
摘要： A capacitor has a MOS gate structure in which a gate insulating film is held between a gate terminal and a ground terminal as a dielectric. A switch unit is connected between the gate terminal and a power supply. The ground terminal is connected to a ground. A switch control circuit that switches a state of the switch unit between a conductive state and a nonconductive state is provided. A predetermined voltage and a voltage of the gate terminal are input to a non-inverting input terminal and an inverting input terminal of the switch control circuit, respectively. The switch unit is conductive when the voltage of the gate terminal is higher than the predetermined voltage, and nonconductive when the voltage of the gate terminal is lower than the predetermined voltage.
摘要翻译：电容器具有MOS栅极结构，其中栅极绝缘膜保持在栅极端子和接地端子之间作为电介质。开关单元连接在栅极端子和电源之间。接地端子接地。提供了一种在导通状态和非导通状态之间切换开关单元的状态的开关控制电路。栅极端子的预定电压和电压分别输入到开关控制电路的非反相输入端子和反相输入端子。当栅极端子的电压高于预定电压时，开关单元导通，并且当栅极端子的电压低于预定电压时，开关单元导通。

8. 发明申请

US20070257371A1 Semiconductor device having a guard ring 有权
公开(公告)号：US20070257371A1
公开(公告)日：2007-11-08
申请号：US11822462
申请日：2007-07-06
申请人： Shigetoshi Wakayama , Mutsuaki Kai , Hiroyuki Kato , Masato Suga
发明人： Shigetoshi Wakayama , Mutsuaki Kai , Hiroyuki Kato , Masato Suga
IPC分类号： H01L23/52
CPC分类号： H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A multilayer interconnection structure of a semiconductor device includes a first guard ring extending continuously along a periphery of a substrate and a second guard ring extending continuously in the multilayer interconnection structure along the periphery so as to be encircled by the first guard ring and so as to encircle an interconnection pattern inside the multilayer interconnection structure, wherein the first and second guard rings are connected with each other mechanically and continuously by a bridging conductor pattern extending continuously in a band form along a region including the first and second guard rings when viewed in the direction perpendicular to the substrate.

9. 发明申请

US20060061409A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060061409A1
公开(公告)日：2006-03-23
申请号：US11042090
申请日：2005-01-26
申请人： Shigetoshi Wakayama , Mutsuaki Kai
发明人： Shigetoshi Wakayama , Mutsuaki Kai
IPC分类号： G11C5/14
CPC分类号： H03F3/45183 , H03F1/52 , H03F1/523 , H03F3/45475
摘要： A capacitor has a MOS gate structure in which a gate insulating film is held between a gate terminal and a ground terminal as a dielectric. A switch unit is connected between the gate terminal and a power supply. The ground terminal is connected to a ground. A switch control circuit that switches a state of the switch unit between a conductive state and a nonconductive state is provided. A predetermined voltage and a voltage of the gate terminal are input to a non-inverting input terminal and an inverting input terminal of the switch control circuit, respectively. The switch unit is conductive when the voltage of the gate terminal is higher than the predetermined voltage, and nonconductive when the voltage of the gate terminal is lower than the predetermined voltage.
摘要翻译：电容器具有MOS栅极结构，其中栅极绝缘膜保持在栅极端子和接地端子之间作为电介质。开关单元连接在栅极端子和电源之间。接地端子接地。提供了一种在导通状态和非导通状态之间切换开关单元的状态的开关控制电路。栅极端子的预定电压和电压分别输入到开关控制电路的非反相输入端子和反相输入端子。当栅极端子的电压高于预定电压时，开关单元导通，并且当栅极端子的电压低于预定电压时，开关单元导通。

10. 发明授权

US06493394B2 SIGNAL TRANSMISSION SYSTEM FOR TRANSMITTING SIGNALS BETWEEN LSI CHIPS, RECEIVER CIRCUIT FOR USE IN THE SIGNAL TRANSMISSION SYSTEM, AND SEMICONDUCTOR MEMORY DEVICE APPLYING THE SIGNAL TRANSMISSION SYSTEM 有权
公开(公告)号：US06493394B2
公开(公告)日：2002-12-10
申请号：US10076526
申请日：2002-02-19
申请人： Hirotaka Tamura , Miyoshi Saito , Kohtaroh Gotoh , Shigetoshi Wakayama , Junji Ogawa , Hisakatsu Araki , Tsz-shing Cheung
发明人： Hirotaka Tamura , Miyoshi Saito , Kohtaroh Gotoh , Shigetoshi Wakayama , Junji Ogawa , Hisakatsu Araki , Tsz-shing Cheung
IPC分类号： H04B300
CPC分类号： H04L25/0276 , G06F13/4243 , H04L25/0278 , H04L25/0282 , H04L25/0288 , H04L25/497 , Y02D10/14 , Y02D10/151
摘要： A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

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