专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09058207B2 Simulation apparatus, method, and computer-readable recording medium 有权
标题翻译：模拟装置，方法和计算机可读记录介质
公开(公告)号：US09058207B2
公开(公告)日：2015-06-16
申请号：US13198828
申请日：2011-08-05
申请人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
发明人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/4881
摘要： A simulation apparatus is disclosed, including a group switching part. The group switching part refers to a priority management table, which manages priority information of priorities to assign a CPU for multiple groups of tasks stored in a storage area, and changes the priorities of the multiple groups of tasks, when an event occurs to activate a task to be executed in verifying of software by using a simulation.
摘要翻译：公开了包括组切换部分的模拟装置。组切换部是指管理优先级管理表，其管理为存储在存储区域中的多组任务分配CPU的优先级信息，并且在发生事件时激活多个任务组的优先级，以激活通过使用仿真验证软件时执行的任务。

2. 发明申请

US20120204184A1 SIMULATION APPARATUS, METHOD, AND COMPUTER-READABLE RECORDING MEDIUM 有权
标题翻译：模拟装置，方法和计算机可读记录介质
公开(公告)号：US20120204184A1
公开(公告)日：2012-08-09
申请号：US13198828
申请日：2011-08-05
申请人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
发明人： Hiroshi Terashima , Yasuki Nakamura , Ryo Kuya , Tatsuya Yoshino , Masaharu Kimura
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A simulation apparatus is disclosed, including a group switching part. The group switching part refers to a priority management table, which manages priority information of priorities to assign a CPU for multiple groups of tasks stored in a storage area, and changes the priorities of the multiple groups of tasks, when an event occurs to activate a task to be executed in verifying of software by using a simulation.
摘要翻译：公开了包括组切换部分的模拟装置。组切换部是指管理优先级管理表，其管理为存储在存储区域中的多组任务分配CPU的优先级信息，并且在发生事件时激活多个任务组的优先级，以激活通过使用仿真验证软件时执行的任务。

3. 发明申请

US20120089386A1 SIMULATION APPARATUS, COMPUTER-READABLE RECORDING MEDIUM, AND METHOD 有权
标题翻译：模拟装置，计算机可读记录介质和方法
公开(公告)号：US20120089386A1
公开(公告)日：2012-04-12
申请号：US13196485
申请日：2011-08-02
申请人： Ryo KUYA , Yasuki Nakamura , Hiroshi Terashima , Tatsuya Yoshino , Masaharu Kimura
发明人： Ryo KUYA , Yasuki Nakamura , Hiroshi Terashima , Tatsuya Yoshino , Masaharu Kimura
IPC分类号： G06F9/44
CPC分类号： G06F17/5022 , G06F2217/86
摘要： A simulation apparatus is disclosed, including a hardware simulator and a CPU model. The hardware simulator activates one or more logical hardware models for verifying embedded software. The CPU model is one of the one or more logical hardware models which imitates a CPU which executes the embedded software, and to trigger the embedded software to operate without synchronization for each of instructions.
摘要翻译：公开了一种模拟装置，包括硬件模拟器和CPU模型。硬件模拟器激活一个或多个逻辑硬件模型以验证嵌入式软件。 CPU模型是模拟执行嵌入式软件的CPU的一个或多个逻辑硬件模型之一，并且触发嵌入式软件对每个指令进行同步操作。

4. 发明授权

US07953962B2 Multiprocessor system and control method thereof 有权
标题翻译：多处理器系统及其控制方法
公开(公告)号：US07953962B2
公开(公告)日：2011-05-31
申请号：US12585620
申请日：2009-09-18
申请人： Yasuki Nakamura , Takahisa Suzuki , Makiko Ito , Hideo Miyake
发明人： Yasuki Nakamura , Takahisa Suzuki , Makiko Ito , Hideo Miyake
IPC分类号： G06F9/54
CPC分类号： G06F9/54
摘要： A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information.
摘要翻译：根据实施例的多处理器系统包括多个处理器，执行控制单元，用于控制多个处理器的处理和多个处理器之间的数据传输; 以及内部数据存储单元，用于存储指示数据传送状态的数据相关信息。如果在先前的数据传送被注册执行之后处理器的处理的控制流程是固定的，并且需要与之前的数据传送相同的目的地的另一数据传送，则执行控制单元基于数据依赖信息来取消先前的数据传送。

5. 发明授权

US07401204B1 Parallel Processor efficiently executing variable instruction word 有权
标题翻译：并行处理器有效执行可变指令字
公开(公告)号：US07401204B1
公开(公告)日：2008-07-15
申请号：US09654527
申请日：2000-09-01
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
IPC分类号： G06F15/00
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.
摘要翻译：并行处理器对包含在由指令定界信息定界的多个指令字中的每个指令字中的一个或多个基本指令执行高效的并行处理。处理器包括：多个指令执行单元，并行地执行根据相应的所提供的基本指令的处理; 指令读取单元根据指令定界信息逐个取出指令字; 以及指令发布单元，其识别并且根据其选择包含在由指令获取单元获取的每个指令字中的每个基本指令给相应的指令执行单元以执行基本指令。

6. 发明授权

US06889315B2 Processor and method of controlling the same 失效
标题翻译：处理器和控制方法
公开(公告)号：US06889315B2
公开(公告)日：2005-05-03
申请号：US09736357
申请日：2000-12-15
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30087 , G06F9/3832 , G06F9/3842 , G06F9/3861
摘要： The present invention relates to a processor that performs a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations. The present invention also relates to a method of controlling such a processor. This processor includes a history control unit that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address.
摘要翻译：本发明涉及一种在存储操作之前执行加载操作同时避免不明确的存储器参考并且实现高速操作的处理器。本发明还涉及一种控制这种处理器的方法。该处理器包括历史控制单元，其存储通过执行在第二指令之前放置的第一指令之前执行的第二指令而获得的结果的存储目的地。当确定要由第一指令处理的第一数据的地址被包括在要由第二指令处理的第二数据的地址区域中时，历史控制单元将通过执行第一指令获得的结果覆盖第二个数据对应地址。

7. 发明授权

US06775762B1 Processor and processor system 失效
标题翻译：处理器和处理器系统
公开(公告)号：US06775762B1
公开(公告)日：2004-08-10
申请号：US09657349
申请日：2000-09-07
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a processor system having a main processor that efficiently executes coprocessor instructions, regardless of the type of each coprocessor to which the main processor is connected. When a coprocessor instruction to instruct execution by a coprocessor is supplied, the main processor determines whether or not the supplied coprocessor instruction has a possibility of having control dependency on a preceding coprocessor instruction being executed by a corresponding one of the coprocessor, in accordance with an instruction field corresponding to the supplied coprocessor instruction. If the supplied coprocessor instruction has the possibility of having the control dependency, the main processor issues the supplied coprocessor to the corresponding one of the processors only after the execution of the preceding coprocessor instruction is completed.
摘要翻译：本发明提供一种具有主处理器的处理器系统，该处理器无论主处理器连接到的每个协处理器的类型如何，都能高效地执行协处理器指令。当提供指示由协处理器执行的协处理器指令时，主处理器确定所提供的协处理器指令是否具有对由协处理器中的相应协处理器执行的先前协处理器指令的控制依赖性的可能性，指令字段对应于提供的协处理器指令。如果所提供的协处理器指令具有控制依赖性的可能性，则只有在前一个协处理器指令的执行完成之后，主处理器才将所提供的协处理器发送给相应的一个处理器。

8. 发明授权

US06681280B1 Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interrupt 有权
标题翻译：中断控制装置和方法分别保持处理器在正常或中断中断之前的相应操作信息
公开(公告)号：US06681280B1
公开(公告)日：2004-01-20
申请号：US09678732
申请日：2000-10-04
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F1324
CPC分类号： G06F9/4812 , G06F13/24
摘要： When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
摘要翻译：当正常中断发生时，在正常中断之前的处理器操作的数据被保存在正常的返回地址寄存器（452），正常的先前状态寄存器（453）和正常因子寄存器（454）中。当发生中断中断时，中断中断前的处理器操作数据保存在另一个中断返回地址寄存器（455）中。因此，即使在正常中断的中断禁止期间，中断也可能发生。此外，当发生中断中断时，中断中断状态被设置在标志寄存器（456）中。通过参考标志寄存器（456）执行中断返回指令，可以准确地恢复中断中断前或正常中断前的操作数据。

9. 发明申请

US20100169068A1 SIMULATION PROGRAM AND SIMULATION APPARATUS 有权
标题翻译：仿真程序和仿真设备
公开(公告)号：US20100169068A1
公开(公告)日：2010-07-01
申请号：US12618137
申请日：2009-11-13
申请人： Ryo Kuya , Yasuki Nakamura , Tatsuya Yoshino
发明人： Ryo Kuya , Yasuki Nakamura , Tatsuya Yoshino
IPC分类号： G06F13/14
CPC分类号： G06F13/105 , G06F9/455
摘要： A simulation program stored in a computer readable recording medium to execute a simulation of first and second simulation objects is provided. The simulation program includes a storage that stores one of an initial state, a read waiting state and a write waiting state for a channel used for data transfer between the first and second simulation objects; a receiver that receives a read request from the first simulation object to the second simulation object through the channel; a judgment unit which, upon reception of the read request, judges whether a state corresponding to the channel is the read waiting state; a transmitter which transmits data corresponding to the channel stored in a storage area to the first simulation object when judging to be the read waiting state; and a changer that changes the state to the initial state based on the data transmission.
摘要翻译：提供存储在计算机可读记录介质中以执行第一和第二仿真对象的模拟的仿真程序。模拟程序包括存储在第一和第二仿真对象之间存储用于数据传输的信道的初始状态，读等待状态和写等待状态之一; 接收器，其通过所述通道从所述第一仿真对象接收到所述第二仿真对象的读取请求; 判断单元，在接收到所述读取请求时，判断与所述通道相对应的状态是否为所述读取等待状态; 当判断为所述读取等待状态时，将与存储在存储区域中的所述通道相对应的数据发送到所述第一模拟对象的发送器; 以及基于数据传输将状态改变为初始状态的更换器。

10. 发明申请

US20100070739A1 Multiprocessor system and control method thereof 有权
标题翻译：多处理器系统及其控制方法
公开(公告)号：US20100070739A1
公开(公告)日：2010-03-18
申请号：US12585620
申请日：2009-09-18
申请人： Yasuki Nakamura , Takahisa SUZUKI , Makiko ITO , Hideo MIYAKE
发明人： Yasuki Nakamura , Takahisa SUZUKI , Makiko ITO , Hideo MIYAKE
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/54
摘要： A multiprocessor system according to an embodiment comprises a plurality of processors, an execution control unit to control processing by the plurality of processors and data transfer between the plurality of processors; and an internal data storage unit to store data dependence information indicating status of the data transfer. If control flow of processing by a processor is fixed after a preceding data transfer is registered for execution and another data transfer to a similar destination as the preceding data transfer is necessary, the execution control unit cancels the preceding data transfer based on the data dependence information.
摘要翻译：根据实施例的多处理器系统包括多个处理器，执行控制单元，用于控制多个处理器的处理和多个处理器之间的数据传送; 以及内部数据存储单元，用于存储指示数据传送状态的数据相关信息。如果在先前的数据传送被注册执行之后处理器的处理的控制流程是固定的，并且需要与之前的数据传送相同的目的地的另一数据传送，则执行控制单元基于数据依赖信息来取消先前的数据传送。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式