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1. 发明授权

US06868472B1 Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memory 失效
标题翻译：控制和寻址作为随机地址存储器以增加对主存储器的访问速度的高速缓冲存储器的方法
公开(公告)号：US06868472B1
公开(公告)日：2005-03-15
申请号：US09671117
申请日：2000-09-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Teruhiko Kamigata , Hitoshi Yoda , Hiroshi Okano , Yoshio Hirose
IPC分类号： G06F12/08 , G06F12/12 , G06F12/00
CPC分类号： G06F12/0802 , G06F2212/2515
摘要： In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.
摘要翻译：在本发明的高速缓冲存储器控制方法和计算机中，高速缓存存储器连接到主存储器并被分成多个高速缓存块，并且锁定/解锁信号被提供给高速缓冲存储器以设置替换抑制禁止将至少一个高速缓存块替换为主存储器的至少一个缓存块的状态，或者重置至少一个高速缓冲存储器时钟的替换禁止状态，使得更换高速缓存中的至少一个阻塞到主内存是允许的。通过使用高速缓冲存储器的其余高速缓冲存储器（除了至少一个高速缓存块之外）来执行读取或写入主存储器，使得当通过锁定/解锁信号设置替换禁止状态时，在主存储器的读取或写入期间禁止将至少一个缓存块替换到主存储器。

2. 发明授权

US07134004B1 Processing device for buffering sequential and target sequences and target address information for multiple branch instructions 失效
标题翻译：用于缓冲顺序和目标序列的处理设备以及多个分支指令的目标地址信息
公开(公告)号：US07134004B1
公开(公告)日：2006-11-07
申请号：US09666853
申请日：2000-09-20
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
摘要翻译：信息处理装置通过流水线处理从指令存储部分读取，缓冲，解码和执行指令，包括：向指令存储部分分配读取地址的指令读取请求部分，包括多个指令缓冲器的指令缓冲部分，缓冲从指令存储部分读取的指令序列; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行。分支指令检测部分检测从指令存储部分读取的指令序列中的分支指令。分支目标地址信息缓冲部分包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息。

3. 发明申请

US20060224870A1 Information processing device 审中-公开
标题翻译：信息处理装置
公开(公告)号：US20060224870A1
公开(公告)日：2006-10-05
申请号：US11444221
申请日：2006-05-31
申请人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
发明人： Shin-ichiro Tago , Taizo Sato , Yoshimasa Takebe , Yasuhiro Yamazaki , Teruhiko Kamigata , Atsuhiro Suga , Hiroshi Okano , Hitoshi Yoda
IPC分类号： G06F9/00
CPC分类号： G06F9/3804 , G06F9/3806 , G06F9/3846
摘要： The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.
摘要翻译：本发明的定义在于，通过流水线处理从指令存储部分读取，缓冲，解码和执行指令的信息处理设备包括：指令读取请求部分，其向指令存储部分分配读取地址; 指令缓冲部分，包括缓冲从指令存储部分读取的指令序列的多个指令缓冲器; 指令执行单元，其对由指令缓冲部分缓冲的指令进行解码和执行; 分支指令检测部分，其检测从指令存储部分读取的指令序列中的分支指令; 以及分支目标地址信息缓冲部分，包括多个分支目标地址信息缓冲器，当分支指令检测部分已经检测到分支指令时，缓冲用于生成分支指令的分支目标地址的转移目标地址信息; 其中，当分支指令检测部分已经检测到分支指令时，分支指令的分支目标地址信息被存储在多个分支目标地址信息缓冲器中的一个中，或分支指令的分支目标指令序列被存储除了存储在分支目标地址信息缓冲器之外，还包括在多个指令缓冲器之一中。

4. 发明申请

US20050289334A1 Method for loading multiprocessor program 审中-公开
标题翻译：加载多处理器程序的方法
公开(公告)号：US20050289334A1
公开(公告)日：2005-12-29
申请号：US11135659
申请日：2005-05-24
申请人： Tomohiro Yamana , Teruhiko Kamigata , Hideo Miyake , Atsuhiro Suga
发明人： Tomohiro Yamana , Teruhiko Kamigata , Hideo Miyake , Atsuhiro Suga
IPC分类号： G06F9/445 , G06F15/167 , G06F15/177
CPC分类号： G06F9/445
摘要： In a computer system having a plurality of processing elements (PE#0 to PE#n) and adopting a distributed-shared-memory-type multiprocessor scheme, a master PE (for example, PE#0) executing a multi PE loader transfers an MPMD program for PE#k to a predetermined area of memory space of PE#0 to which a unique memory (LM) of PE#k is temporally allocated. The LMs of PE#1 to PE#n can be allocated to different areas of the memory space of PE#0 respectively, or can be allocated the same area thereof.
摘要翻译：在具有多个处理元件（PE＃0〜PE＃n）并且采用分布式共享存储器型多处理器方案的计算机系统中，执行多PE加载器的主机PE（例如，PE＃0）用于PE＃k的MPMD程序到PE＃0的唯一存储器（LM）临时分配到的PE＃0的存储空间的预定区域。 PE＃1〜PE＃n的LM可以分配给PE＃0的存储空间的不同区域，也可以分配相同的区域。

5. 发明申请

US20080215859A1 Computer with high-speed context switching 审中-公开
标题翻译：具有高速上下文切换的计算机
公开(公告)号：US20080215859A1
公开(公告)日：2008-09-04
申请号：US12073042
申请日：2008-02-28
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Masayuki Tsuji , Yasuhiro Yamazaki , Yoshimasa Takebe , Taizo Sato , Shinichiro Tago
IPC分类号： G06F9/312 , G06F9/302
CPC分类号： G06F7/535 , G06F9/3001 , G06F9/30043 , G06F9/3013 , G06F9/3814 , G06F9/3836 , G06F9/3857 , G06F9/3861 , G06F9/3867 , G06F9/3877 , G06F9/461 , G06F9/5016 , G06F2207/5353 , Y02D10/22
摘要： A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.
摘要翻译：以时分方式执行多个程序的并行处理的计算机包括划分为多个区域的硬件资源，记录识别第一程序的识别信息的撤离单元，以及排除存储在所述多个区域的区域中的信息如果该区域是执行第二程序所必需的并被用于执行第一程序的区域，以及恢复单元，其在第二程序停止时基于识别信息将该撤离信息恢复到该区域，或者结束。

6. 发明授权

US07376820B2 Information processing unit, and exception processing method for specific application-purpose operation instruction 有权
标题翻译：信息处理单元和特殊应用目的操作指令的异常处理方法
公开(公告)号：US07376820B2
公开(公告)日：2008-05-20
申请号：US09741802
申请日：2000-12-22
申请人： Michihide Kimura , Atsuhiro Suga , Hideo Miyake , Satoshi Imai , Yasuki Nakamura
发明人： Michihide Kimura , Atsuhiro Suga , Hideo Miyake , Satoshi Imai , Yasuki Nakamura
IPC分类号： G06F9/44 , G06F9/54
CPC分类号： G06F9/3838 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3879
摘要： In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.
摘要翻译：在处理器核心中，在控制部分中提供不指定功能规格的操作指令和用于处理特定应用目的操作指令的单元。该单元的结构可以基于灵活的管道结构进行更改，并为每个应用领域单独设计。在处理器核心中还设置有从上述单元的指令发出到可以利用结果的延迟的寄存器，以防止输出端口的争用。规定与发布上述单元的指令的间隔的约束有关的延迟的另一个寄存器也被提供在处理器核心中，以便防止具有前面指令的资源的争用。

7. 发明授权

US07581090B2 Interrupt control apparatus and method 有权
标题翻译：中断控制装置及方法
公开(公告)号：US07581090B2
公开(公告)日：2009-08-25
申请号：US10692800
申请日：2003-10-27
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F9/00
CPC分类号： G06F9/4812 , G06F13/24
摘要： When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.
摘要翻译：当正常中断发生时，在正常中断之前的处理器操作的数据被保存在正常的返回地址寄存器（452），正常的先前状态寄存器（453）和正常因子寄存器（454）中。当发生中断中断时，中断中断前的处理器操作数据保存在另一个中断返回地址寄存器（455）中。因此，即使在正常中断的中断禁止期间，中断也可能发生。此外，当发生中断中断时，中断中断状态被设置在标志寄存器（456）中。通过参考标志寄存器（456）执行中断返回指令，可以准确地恢复中断中断前或正常中断前的操作数据。

8. 发明授权

US07401204B1 Parallel Processor efficiently executing variable instruction word 有权
标题翻译：并行处理器有效执行可变指令字
公开(公告)号：US07401204B1
公开(公告)日：2008-07-15
申请号：US09654527
申请日：2000-09-01
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura , Yoshimasa Takebe
IPC分类号： G06F15/00
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3853
摘要： A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.
摘要翻译：并行处理器对包含在由指令定界信息定界的多个指令字中的每个指令字中的一个或多个基本指令执行高效的并行处理。处理器包括：多个指令执行单元，并行地执行根据相应的所提供的基本指令的处理; 指令读取单元根据指令定界信息逐个取出指令字; 以及指令发布单元，其识别并且根据其选择包含在由指令获取单元获取的每个指令字中的每个基本指令给相应的指令执行单元以执行基本指令。

9. 发明授权

US06889315B2 Processor and method of controlling the same 失效
标题翻译：处理器和控制方法
公开(公告)号：US06889315B2
公开(公告)日：2005-05-03
申请号：US09736357
申请日：2000-12-15
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/30087 , G06F9/3832 , G06F9/3842 , G06F9/3861
摘要： The present invention relates to a processor that performs a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations. The present invention also relates to a method of controlling such a processor. This processor includes a history control unit that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address.
摘要翻译：本发明涉及一种在存储操作之前执行加载操作同时避免不明确的存储器参考并且实现高速操作的处理器。本发明还涉及一种控制这种处理器的方法。该处理器包括历史控制单元，其存储通过执行在第二指令之前放置的第一指令之前执行的第二指令而获得的结果的存储目的地。当确定要由第一指令处理的第一数据的地址被包括在要由第二指令处理的第二数据的地址区域中时，历史控制单元将通过执行第一指令获得的结果覆盖第二个数据对应地址。

10. 发明授权

US06775762B1 Processor and processor system 失效
标题翻译：处理器和处理器系统
公开(公告)号：US06775762B1
公开(公告)日：2004-08-10
申请号：US09657349
申请日：2000-09-07
申请人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
发明人： Hideo Miyake , Atsuhiro Suga , Yasuki Nakamura
IPC分类号： G06F938
CPC分类号： G06F9/3861 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a processor system having a main processor that efficiently executes coprocessor instructions, regardless of the type of each coprocessor to which the main processor is connected. When a coprocessor instruction to instruct execution by a coprocessor is supplied, the main processor determines whether or not the supplied coprocessor instruction has a possibility of having control dependency on a preceding coprocessor instruction being executed by a corresponding one of the coprocessor, in accordance with an instruction field corresponding to the supplied coprocessor instruction. If the supplied coprocessor instruction has the possibility of having the control dependency, the main processor issues the supplied coprocessor to the corresponding one of the processors only after the execution of the preceding coprocessor instruction is completed.
摘要翻译：本发明提供一种具有主处理器的处理器系统，该处理器无论主处理器连接到的每个协处理器的类型如何，都能高效地执行协处理器指令。当提供指示由协处理器执行的协处理器指令时，主处理器确定所提供的协处理器指令是否具有对由协处理器中的相应协处理器执行的先前协处理器指令的控制依赖性的可能性，指令字段对应于提供的协处理器指令。如果所提供的协处理器指令具有控制依赖性的可能性，则只有在前一个协处理器指令的执行完成之后，主处理器才将所提供的协处理器发送给相应的一个处理器。

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