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1. 发明申请

US20060065909A1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
公开(公告)号：US20060065909A1
公开(公告)日：2006-03-30
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00 , H01L21/84 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/20
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.

2. 发明授权

US07018877B1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
标题翻译：通过界面粘合能量对比和由此形成的薄膜晶体管器件来选择性地分层薄膜
公开(公告)号：US07018877B1
公开(公告)日：2006-03-28
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
IPC分类号： H01L21/77 , H01L29/786
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.
摘要翻译：根据本发明的系统和方法的各种示例性实施例提供了一种制造自对准薄膜晶体管的方法，所述晶体管包括覆盖掺杂层的至少一部分的金属层，所述掺杂层覆盖至少一部分在金属层中产生的应变，该方法包括蚀刻掺杂层的暴露部分以在掺杂层和电介质层之间的界面产生缺陷，以引发掺杂层的分层从电介质层。当缺陷传播到具有大于金属层的应变的粘合能量的掺杂层和电介质层之间的界面时，阻止掺杂层从电介质层的分层。

3. 发明授权

US07884361B2 Pattern-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07884361B2
公开(公告)日：2011-02-08
申请号：US12817127
申请日：2010-06-16
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

4. 发明申请

US20070026585A1 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US20070026585A1
公开(公告)日：2007-02-01
申请号：US11193847
申请日：2005-07-28
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

5. 发明授权

US07804090B2 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07804090B2
公开(公告)日：2010-09-28
申请号：US12018794
申请日：2008-01-23
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L29/04
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

6. 发明申请

US20060063369A1 Sub-resolution gaps generated by controlled over-etching 有权
标题翻译：通过控制过蚀刻产生的子分辨率间隙
公开(公告)号：US20060063369A1
公开(公告)日：2006-03-23
申请号：US10943624
申请日：2004-09-17
申请人： JengPing Lu , Jackson Ho , Chinwen Shih , Michael Chabinyc , William Wong
发明人： JengPing Lu , Jackson Ho , Chinwen Shih , Michael Chabinyc , William Wong
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L21/76838 , B82Y30/00 , H01L21/28506 , H01L27/124
摘要： Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.
摘要翻译：控制过蚀刻用于产生具有小于用于产生金属图案的特征图案化（例如，光刻）工艺的分辨率限制的间隙的金属图案。第一金属层被形成并被掩蔽，并且暴露的区域被蚀刻掉。允许蚀刻处理以受控的方式继续，以产生期望量的过蚀刻（即，底切掩模），使得第一金属层的边缘以预定的间隙距离偏离掩模的边缘。然后沉积第二金属层，使得第二金属层的边缘与第一金属层隔开预定的间隙距离。金属间隙用于限定例如晶体管沟道长度，由此有助于生产具有小于工艺分辨率极限的蚀刻工艺控制定义的沟道长度的晶体管。

7. 发明授权

US07749916B2 Additive printed mask process and structures produced thereby 有权
标题翻译：添加印刷掩模工艺和由此生产的结构
公开(公告)号：US07749916B2
公开(公告)日：2010-07-06
申请号：US12046242
申请日：2008-03-11
申请人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
发明人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
IPC分类号： H01L21/31
CPC分类号： G02F1/133512 , B41M3/003 , B41M3/006 , G02F1/133516 , G03F7/2018 , Y10S438/942
摘要： A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
摘要翻译：数字光刻工艺首先沉积由印刷图案掩模特征组成的掩模层。印刷图案掩模特征限定了可以沉积目标材料的间隙，优选通过数字光刻工艺。如果需要，目标材料被固化或硬化成目标特征。然后选择性地去除掩模层。剩余的目标特征然后可以用作曝光或蚀刻掩模，诸如流体容纳元件的物理结构等。可以在实现数字光刻的优点的同时获得精细特征宽度，更小的打印图案化掩模特征的最小宽度制造过程。

8. 发明申请

US20070172969A1 Additive printed mask process and structures produced thereby 有权
标题翻译：添加印刷掩模工艺和由此生产的结构
公开(公告)号：US20070172969A1
公开(公告)日：2007-07-26
申请号：US10536102
申请日：2006-01-20
申请人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
发明人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
IPC分类号： H01L21/00
CPC分类号： G02F1/133512 , B41M3/003 , B41M3/006 , G02F1/133516 , G03F7/2018 , Y10S438/942
摘要： A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
摘要翻译：数字光刻工艺首先沉积由印刷图案掩模特征组成的掩模层。印刷图案掩模特征限定了可以沉积目标材料的间隙，优选通过数字光刻工艺。如果需要，目标材料被固化或硬化成目标特征。然后选择性地去除掩模层。剩余的目标特征可以用作曝光或蚀刻掩模，诸如流体容纳元件的物理结构等。可以在实现数字光刻的优点的同时获得精细特征宽度，打印图案化掩模特征的最小宽度更窄制造过程。

9. 发明申请

US20050136358A1 Patterning using wax printing and lift off 有权
标题翻译：图案使用蜡印刷和剥离
公开(公告)号：US20050136358A1
公开(公告)日：2005-06-23
申请号：US10741252
申请日：2003-12-19
申请人： Kateri Paul , William Wong , Steven Ready , Rene Lujan
发明人： Kateri Paul , William Wong , Steven Ready , Rene Lujan
IPC分类号： H01L21/28 , G03F7/00 , H01L21/027 , H01L21/033 , H01L21/306 , H01L21/311 , H01L21/336 , H01L21/768 , H01L29/786
CPC分类号： H01L21/31144 , H01L21/0272 , H01L21/0335 , H01L21/76802
摘要： A method for performing a liftoff operation involves printing a liftoff pattern using low-resolution patterning techniques to form fine feature patterns. The resulting feature size is defined by the spacing between printed patterns rather than the printed pattern size. By controlling the cross-sectional profile of the printed liftoff pattern, mask structures may be formed from the liftoff operation having beneficial etch-mask aperture profiles. For example, a multi-layer printed liftoff pattern can be used to create converging aperture profiles in a patterned layer. The patterned layer can then be used as an etch mask, where the converging aperture profiles result in desirable diverging etched features.
摘要翻译：用于执行提升操作的方法包括使用低分辨率图案化技术打印提升图案以形成精细的特征图案。所得到的特征尺寸由印刷图案之间的间距而不是印刷图案尺寸定义。通过控制印刷的剥离图案的横截面轮廓，可以从具有有利的蚀刻掩模孔径轮廓的提升操作形成掩模结构。例如，可以使用多层印刷提升图案来在图案化层中形成会聚孔径轮廓。然后可以将图案化层用作蚀刻掩模，其中会聚孔径轮廓导致期望的发散蚀刻特征。

10. 发明申请

US20070235410A1 Method of forming a darkfield etch mask 失效
标题翻译：形成暗场蚀刻掩模的方法
公开(公告)号：US20070235410A1
公开(公告)日：2007-10-11
申请号：US11394438
申请日：2006-03-31
申请人： William Wong , Scott Limb , Beverly Russo , Michael Chabinyc , Rene Lujan
发明人： William Wong , Scott Limb , Beverly Russo , Michael Chabinyc , Rene Lujan
IPC分类号： C23F1/00
CPC分类号： B44C1/22 , H01L27/1292 , H01L29/4908
摘要： Susceptibility of darkfield etch masks (majority of the mask area is opaque) to pinhole defects, transferred pattern, non-uniformity, etc. due to ejector dropout or drop misdirection, and long duty cycles due to large-area coverage, when using digital lithography (or print patterning) is addressed by using a clear-field print pattern that is then coated with etch resist material. The printed clear field pattern is selectively removed to form an inverse pattern (darkfield) within the coated resist layer. Etching then removes selected portions of an underlying (e.g., encapsulation, conductive, etc.) layer. Removal of the mask produces a layer with large-area features with substantially reduced defects.
摘要翻译：当使用数字光刻技术时，由于喷射器脱落或滴落错误导向，暗区蚀刻掩模（大部分掩模区域不透明）对针孔缺陷，转印图案，不均匀性等的敏感性以及由于大面积覆盖而造成的长占空比（或印刷图案化）通过使用随后涂覆有抗蚀剂材料的透明场印刷图案来解决。选择性地去除打印的清晰场图案以在涂覆的抗蚀剂层内形成反向图案（暗场）。然后蚀刻去除底层（例如，封装，导电等）层的选定部分。去除掩模产生具有大面积特征并具有显着减少的缺陷的层。

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