专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100252927A1 Pattern-Print Thin-Film Transistors with Top Gate Geometry 有权
标题翻译：带顶栅几何图案印刷薄膜晶体管
公开(公告)号：US20100252927A1
公开(公告)日：2010-10-07
申请号：US12817127
申请日：2010-06-16
申请人： William S. Wong , Rene A. Lujan , Eugene M. Chow
发明人： William S. Wong , Rene A. Lujan , Eugene M. Chow
IPC分类号： H01L29/45
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

2. 发明授权

US07566899B2 Organic thin-film transistor backplane with multi-layer contact structures and data lines 有权
标题翻译：具有多层接触结构和数据线的有机薄膜晶体管背板
公开(公告)号：US07566899B2
公开(公告)日：2009-07-28
申请号：US11316551
申请日：2005-12-21
申请人： Michael L. Chabinyc , Rene A Lujan , Ana Claudia Arias , Jackson H. Ho
发明人： Michael L. Chabinyc , Rene A Lujan , Ana Claudia Arias , Jackson H. Ho
IPC分类号： H01L51/10 , G02F1/1345
CPC分类号： H01L27/283 , H01L51/0037 , H01L51/0541 , H01L51/0545 , H01L51/105
摘要： A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.
摘要翻译：背板电路包括有机薄膜晶体管（OTFT）的阵列，每个OTFT包括源极接触，漏极接触以及在源极和漏极接触之间延伸的有机半导体区域。每行的漏极触点连接到地址线。源极和漏极触点和地址线使用包括由相对便宜的金属（例如，铝或铜）形成的相对厚的基部的多层结构以及由高功函数形成的相对较薄的接触层制造，与有机半导体呈现良好的电接触的低氧化金属（例如，金）形成在与基底的至少一个外表面相对的位置，并且至少部分地位于有机半导体与下面的介电层接触的界面区域中。

3. 发明授权

US6140668A Silicon structures having an absorption layer 失效
标题翻译：具有吸收层的硅结构
公开(公告)号：US6140668A
公开(公告)日：2000-10-31
申请号：US69055
申请日：1998-04-28
申请人： Ping Mei , Rene A. Lujan
发明人： Ping Mei , Rene A. Lujan
IPC分类号： H01L21/77 , H01L21/84 , H01L27/12 , H01L29/76 , H01L29/04
CPC分类号： H01L27/1214
摘要： Amorphous and polycrystalline silicon (hybrid) devices are formed close to one another employing laser crystallization and back side lithography processes. A mask (e.g., TiW) is used to protect the amorphous silicon device during laser crystallization. A patterned nitride layer is used to protect the amorphous silicon device during rehydrogenation of the polycrystalline silicon. An absorption film (e.g., amorphous silicon) is used to compensate for the different transparencies of amorphous and polycrystalline silicon during the back side lithography. Device spacing of between 2 and 50 micrometers may be obtained, while using materials and process steps otherwise compatible with existing hybrid device formation processes.
摘要翻译：使用激光结晶和背面光刻工艺，非晶和多晶硅（混合）器件彼此靠近地形成。在激光结晶期间，使用掩模（例如TiW）来保护非晶硅器件。在多晶硅的再氢化期间，使用图案化的氮化物层来保护非晶硅器件。吸收膜（例如，非晶硅）用于补偿背面光刻期间的非晶硅和多晶硅的不同透明度。可以获得2至50微米之间的器件间隔，同时使用与现有的混合器件形成工艺相适应的材料和工艺步骤。

4. 发明申请

US20090159940A1 STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US20090159940A1
公开(公告)日：2009-06-25
申请号：US11963008
申请日：2007-12-21
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

5. 发明授权

US6107641A Thin film transistor with reduced parasitic capacitance and reduced feed-through voltage 失效
标题翻译：具有降低的寄生电容和降低的馈通电压的薄膜晶体管
公开(公告)号：US6107641A
公开(公告)日：2000-08-22
申请号：US927023
申请日：1997-09-10
申请人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
发明人： Ping Mei , Rene A. Lujan , James B. Boyce , Christopher L. Chua , Michael G. Hack
IPC分类号： H01L21/223 , H01L21/225 , H01L21/266 , H01L21/336 , H01L27/144 , H01L27/146 , H01L29/786 , H01L31/0216 , H01L29/76
CPC分类号： H01L29/78696 , H01L21/223 , H01L21/2236 , H01L21/2254 , H01L21/2255 , H01L21/266 , H01L27/1443 , H01L27/14603 , H01L29/66757 , H01L29/66765 , H01L29/78669 , H01L31/02162 , H01L31/02165 , Y10S438/94
摘要： An improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser doping technique is applied to fabricate such transistors. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.
摘要翻译：提供了不具有源极/栅极或漏极/栅极重叠的改进的薄膜晶体管结构。应用激光掺杂技术来制造这种晶体管。消除源极/栅极和漏极/栅极重叠显着降低或消除了源极和栅极之间的寄生电容和馈通电压。可以获得具有高场效应迁移率的短沟道a-Si：H薄膜晶体管。提供了改进的像素性能和像素到像素的均匀性。

6. 发明授权

US5733804A Fabricating fully self-aligned amorphous silicon device 失效
标题翻译：制造完全自对准非晶硅器件
公开(公告)号：US5733804A
公开(公告)日：1998-03-31
申请号：US577634
申请日：1995-12-22
申请人： Michael G. Hack , Rene A. Lujan
发明人： Michael G. Hack , Rene A. Lujan
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786
CPC分类号： H01L29/78696 , H01L27/1214 , H01L29/66765 , Y10S438/949
摘要： An amorphous silicon thin film transistor (a-Si TFT) or other a-Si device is produced by depositing and lithographically patterning a layer of doped semiconductor material such as microcrystalline or polycrystalline silicon to produce a conductive lead. The semiconductor material is deposited over an insulating region and over an exposed part of an amorphous silicon layer. The insulating region has an edge that is over and approximately aligned with an edge of a gate region. The doped semiconductor layer therefore forms a junction to the amorphous silicon layer at the edge of the insulating region, approximately aligned with the edge of the gate region. Self-aligned lithographic patterning is performed in such a way that the conductive lead overlaps the insulating region by a distance that is no more than a maximum overlap distance. The maximum overlap distance can, for example, be no more than 1.0 .mu.m, and can be 0.5 .mu.m. The insulating region and the doped semiconductor layer can both be lithographically patterned by a combination of self-aligned backside exposure and top masked exposure. Overlap distance can be controlled by timing backside exposure, application of developer, baking, or application of etchant.
摘要翻译：通过对诸如微晶或多晶硅的掺杂半导体材料的层进行沉积和光刻图案来制造非晶硅薄膜晶体管（a-Si TFT）或其它a-Si器件，以产生导电引线。半导体材料沉积在非晶硅层的绝缘区域和暴露部分之上。绝缘区域具有在栅极区域的边缘上方且大致对齐的边缘。因此，掺杂半导体层在绝缘区域的边缘处形成大致与栅极区域的边缘对准的非晶硅层的结。以这样的方式进行自对准平版印刷图案，使得导电引线与绝缘区域重叠不超过最大重叠距离的距离。最大重叠距离例如可以不大于1.0μm，并且可以是0.5μm。绝缘区域和掺杂半导体层可以通过自对准背面曝光和顶部掩模曝光的组合进行光刻图案化。重叠距离可以通过定时背面曝光，显影剂的应用，烘烤或蚀刻剂的应用来控制。

7. 发明授权

US5278028A Process for fabricating multi-discrete-phase fresnel lenses 失效
标题翻译：制造多分散相菲涅尔透镜的工艺
公开(公告)号：US5278028A
公开(公告)日：1994-01-11
申请号：US796742
申请日：1991-11-25
申请人： Babur B. Hadimioglu , Rene A. Lujan
发明人： Babur B. Hadimioglu , Rene A. Lujan
IPC分类号： G02B3/08 , G02B5/18 , G03F7/00 , G03C5/00
CPC分类号： G02B3/08 , G02B5/1876 , G03F7/001
摘要： A process is provided for fabricating multi-discrete-phase binary Fresnel acoustic and optical lenses through the use of standard microelectronic fabrication techniques, thereby enabling such lenses to be produced repeatedly and economically to exacting design specifications.
摘要翻译：提供了一种通过使用标准微电子制造技术来制造多分离相位二进制菲涅尔声和光学透镜的过程，从而使这种透镜能够以严格的设计规范重复和经济地制造。

8. 发明授权

US07824949B2 Structure and method for flexible sensor array 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US07824949B2
公开(公告)日：2010-11-02
申请号：US11963008
申请日：2007-12-21
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L21/00
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

9. 发明申请

US20100181604A1 STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US20100181604A1
公开(公告)日：2010-07-22
申请号：US12692379
申请日：2010-01-22
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L27/146
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

10. 发明授权

US07018877B1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
标题翻译：通过界面粘合能量对比和由此形成的薄膜晶体管器件来选择性地分层薄膜
公开(公告)号：US07018877B1
公开(公告)日：2006-03-28
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
IPC分类号： H01L21/77 , H01L29/786
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.
摘要翻译：根据本发明的系统和方法的各种示例性实施例提供了一种制造自对准薄膜晶体管的方法，所述晶体管包括覆盖掺杂层的至少一部分的金属层，所述掺杂层覆盖至少一部分在金属层中产生的应变，该方法包括蚀刻掺杂层的暴露部分以在掺杂层和电介质层之间的界面产生缺陷，以引发掺杂层的分层从电介质层。当缺陷传播到具有大于金属层的应变的粘合能量的掺杂层和电介质层之间的界面时，阻止掺杂层从电介质层的分层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式