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1. 发明授权

US07018877B1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
标题翻译：通过界面粘合能量对比和由此形成的薄膜晶体管器件来选择性地分层薄膜
公开(公告)号：US07018877B1
公开(公告)日：2006-03-28
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
IPC分类号： H01L21/77 , H01L29/786
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.
摘要翻译：根据本发明的系统和方法的各种示例性实施例提供了一种制造自对准薄膜晶体管的方法，所述晶体管包括覆盖掺杂层的至少一部分的金属层，所述掺杂层覆盖至少一部分在金属层中产生的应变，该方法包括蚀刻掺杂层的暴露部分以在掺杂层和电介质层之间的界面产生缺陷，以引发掺杂层的分层从电介质层。当缺陷传播到具有大于金属层的应变的粘合能量的掺杂层和电介质层之间的界面时，阻止掺杂层从电介质层的分层。

2. 发明申请

US20060065909A1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
公开(公告)号：US20060065909A1
公开(公告)日：2006-03-30
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00 , H01L21/84 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/20
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.

3. 发明授权

US07884361B2 Pattern-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07884361B2
公开(公告)日：2011-02-08
申请号：US12817127
申请日：2010-06-16
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

4. 发明申请

US20070026585A1 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US20070026585A1
公开(公告)日：2007-02-01
申请号：US11193847
申请日：2005-07-28
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

5. 发明申请

US20070221611A1 Method of manufacturing fine features for thin film transistors 有权
标题翻译：制造薄膜晶体管精细特征的方法
公开(公告)号：US20070221611A1
公开(公告)日：2007-09-27
申请号：US11388731
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
IPC分类号： H01B13/00 , C23F1/00
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292
摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
摘要翻译：一种在晶体管上制造诸如小栅电极的精细特征的工艺。该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

6. 发明授权

US07804090B2 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07804090B2
公开(公告)日：2010-09-28
申请号：US12018794
申请日：2008-01-23
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L29/04
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

7. 发明申请

US20070221610A1 Method using monolayer etch masks in combination with printed masks 失效
标题翻译：使用单层蚀刻掩模与印刷掩模组合的方法
公开(公告)号：US20070221610A1
公开(公告)日：2007-09-27
申请号：US11388718
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： H01L21/302 , H01L21/0271 , H01L21/0273 , H01L27/124 , H01L27/1288 , H01L27/1292 , H01L29/66765
摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
摘要翻译：将薄膜图案尺寸小于印刷像素掩模尺寸的方法。印刷的掩模沉积在基底上的薄膜上。第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。然后将掩模层与蚀刻结合在薄膜上形成图案。形成在薄膜中的特征小于印刷掩模的最小尺寸。涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

8. 发明申请

US20110167526A1 Microsprings Having Nanowire Tip Structures 审中-公开
标题翻译：具有纳米线尖端结构的微管
公开(公告)号：US20110167526A1
公开(公告)日：2011-07-07
申请号：US13045042
申请日：2011-03-10
申请人： Eugene Chow , Pengfei Qi
发明人： Eugene Chow , Pengfei Qi
IPC分类号： G01Q70/08 , B82Y30/00
CPC分类号： B81C1/0015 , B81B2203/019 , B81B2207/07 , B82Y10/00
摘要： A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.
摘要翻译：应力工程微球通常在基底的平面上形成。纳米线（或等效地，纳米管）也在其顶端形成在基板的平面中。一旦形成，可以例如光刻地限定纳米线的长度。然后可以去除位于微弹簧下面的牺牲层，允许微弹簧中的工程应力使结构弯曲出平面，从而使纳米线离开基底并离开平面。由此提供了使用纳米线作为接触。可以将纳米线夹在微弹簧的末端以增加坚固性。在形成过程中可以涂覆纳米线以提供最终装置的附加功能。

9. 发明申请

US20090322845A1 ANISOTROPICALLY CONDUCTIVE BACKSIDE ADDRESSABLE IMAGING BELT FOR USE WITH CONTACT ELECTROGRAPHY 有权
标题翻译：使用联系电子技术的非均匀导电背面可寻址成像带
公开(公告)号：US20090322845A1
公开(公告)日：2009-12-31
申请号：US12145677
申请日：2008-06-25
申请人： Timothy D. Stowe , Chu-heng Liu , Jeng Ping Lu , Eugene Chow , Gregory B. Anderson , Armin Volkel , Eric Peeters
发明人： Timothy D. Stowe , Chu-heng Liu , Jeng Ping Lu , Eugene Chow , Gregory B. Anderson , Armin Volkel , Eric Peeters
IPC分类号： B41J2/41
CPC分类号： B41J2/41 , G03G15/32
摘要： An addressable imaging belt for use in printing applications having embedded anisotropically conductive addressable islands configured for electric contact on a first side of the belt by a write head consisting of an array of compliant cantilevered fingers with contact pads/points to which a voltage can be applied. The conductive addressable islands electrically isolated from one another and extending substantially through the thickness of the belt in order to allow charge to flow through the belt towards a second side of the belt, in order to form a latent electrostatic image on the second side and develop this latent image by attracting colorized toner or other electrically charged particles to the second side.
摘要翻译：一种用于印刷应用的可寻址成像带，其具有嵌入的各向异性导电可寻址岛，其配置用于通过由柔性悬臂指状物阵列组成的写头组成，用于在带的第一侧上进行电接触，所述写头具有可被施加电压的接触焊盘/点。导电寻址岛彼此电隔离并且基本上延伸穿过带的厚度，以便允许电荷通过带流向带的第二侧，以在第二面上形成静电潜像并显影该潜像通过将着色调色剂或其它带电粒子吸引到第二侧。

10. 发明申请

US20070125486A1 Vertically spaced plural microsprings 有权
标题翻译：垂直间隔的多个微弹簧
公开(公告)号：US20070125486A1
公开(公告)日：2007-06-07
申请号：US11292474
申请日：2005-12-02
申请人： Thomas Hantschel , Eugene Chow
发明人： Thomas Hantschel , Eugene Chow
IPC分类号： B32B37/00
CPC分类号： B81B3/001 , B81B2207/07 , B81C1/00666 , B81C1/00952 , G01R1/06722 , G01R1/06727 , G01R1/06744 , G01R3/00 , H05K3/4092
摘要： A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited, either as a single layer or as a composite of multiple sub layers, to have a tailored stress differential along its cross-section. A lower microspring may be made to push up against an upper microspring to provide increased contact force, or push down against a substrate to ensure release during manufacture. The microsprings may be provided with similar stress differentials or opposite stress differentials to obtain desired microspring profiles and functionality. Microsprings may also be physically connected at their distal ends for increased contact force. The microsprings may be formed of electrically conductive material or coated with electrically conductive material for probe card and similar applications.
摘要翻译：提供多个垂直间隔开的微弹簧以增加微弹簧接触力，接触面积，接触可靠性和接触屈服。微珠材料作为单层或作为多个子层的复合材料沉积，沿其横截面具有定制的应力差。可以制备较低的微弹簧以向上推动上部微型弹性体以提供增加的接触力，或者向下推动抵靠基底以确保制造过程中的释放。可以提供类似的应力差异或相反的应力差异以获得所需的微弹体轮廓和功能性。微弹簧也可以在其远端物理连接以增加接触力。微弹簧可以由导电材料形成或涂覆有用于探针卡和类似应用的导电材料。

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