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1. 发明授权

US07018877B1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
标题翻译：通过界面粘合能量对比和由此形成的薄膜晶体管器件来选择性地分层薄膜
公开(公告)号：US07018877B1
公开(公告)日：2006-03-28
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene A. Lujan , Eugene Chow
IPC分类号： H01L21/77 , H01L29/786
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.
摘要翻译：根据本发明的系统和方法的各种示例性实施例提供了一种制造自对准薄膜晶体管的方法，所述晶体管包括覆盖掺杂层的至少一部分的金属层，所述掺杂层覆盖至少一部分在金属层中产生的应变，该方法包括蚀刻掺杂层的暴露部分以在掺杂层和电介质层之间的界面产生缺陷，以引发掺杂层的分层从电介质层。当缺陷传播到具有大于金属层的应变的粘合能量的掺杂层和电介质层之间的界面时，阻止掺杂层从电介质层的分层。

2. 发明申请

US20060065909A1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
公开(公告)号：US20060065909A1
公开(公告)日：2006-03-30
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00 , H01L21/84 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/20
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.

3. 发明授权

US07884361B2 Pattern-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07884361B2
公开(公告)日：2011-02-08
申请号：US12817127
申请日：2010-06-16
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

4. 发明申请

US20070026585A1 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US20070026585A1
公开(公告)日：2007-02-01
申请号：US11193847
申请日：2005-07-28
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

5. 发明申请

US20070221611A1 Method of manufacturing fine features for thin film transistors 有权
标题翻译：制造薄膜晶体管精细特征的方法
公开(公告)号：US20070221611A1
公开(公告)日：2007-09-27
申请号：US11388731
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
IPC分类号： H01B13/00 , C23F1/00
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292
摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
摘要翻译：一种在晶体管上制造诸如小栅电极的精细特征的工艺。该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

6. 发明授权

US07804090B2 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07804090B2
公开(公告)日：2010-09-28
申请号：US12018794
申请日：2008-01-23
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L29/04
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

7. 发明申请

US20070221610A1 Method using monolayer etch masks in combination with printed masks 失效
标题翻译：使用单层蚀刻掩模与印刷掩模组合的方法
公开(公告)号：US20070221610A1
公开(公告)日：2007-09-27
申请号：US11388718
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： H01L21/302 , H01L21/0271 , H01L21/0273 , H01L27/124 , H01L27/1288 , H01L27/1292 , H01L29/66765
摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
摘要翻译：将薄膜图案尺寸小于印刷像素掩模尺寸的方法。印刷的掩模沉积在基底上的薄膜上。第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。然后将掩模层与蚀刻结合在薄膜上形成图案。形成在薄膜中的特征小于印刷掩模的最小尺寸。涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

8. 发明申请

US20070148895A1 Integrateable capacitors and microcoils and methods of making thereof 有权
标题翻译：可集成电容器和微型线圈及其制造方法
公开(公告)号：US20070148895A1
公开(公告)日：2007-06-28
申请号：US11319075
申请日：2005-12-28
申请人： Koenraad Van Schuylenbergh , Eugene Chow , JengPing Lu
发明人： Koenraad Van Schuylenbergh , Eugene Chow , JengPing Lu
IPC分类号： H01L21/00
CPC分类号： H01G5/18 , H01F17/0006 , H01F17/02 , H01F21/04 , H01F27/40 , H01F41/041 , H01L28/10 , H01L28/40
摘要： Methods for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A method for integrally forming a capacitor and a microcoil on a substrate may involve depositing and patterning a dielectric layer on the substrate, depositing and patterning a sacrificial layer on the substrate, depositing and patterning conductive material on the semiconductor substrate, depositing and patterning a polymer layer on the semiconductor substrate, removing an exposed portion of the conductive material exposed by the patterned polymer layer to release a portion of the conductive pattern from the semiconductor substrate to form out-of-plane windings of the microcoil, depositing second conductive material on exposed portions of the conductive material, and removing the sacrificial layer. The patterned conductive material may include a windings portion of the microcoil, an overlapping electrode portion of the capacitor and a support portion for the electrode of the capacitor.
摘要翻译：描述了在衬底上整体形成高Q可调谐电容器和高Q电感器的方法。用于在基板上一体地形成电容器和微线圈的方法可以包括在基板上沉积和图案化电介质层，在衬底上沉积和图案化牺牲层，在半导体衬底上沉积和图案化导电材料，沉积和图案化聚合物去除由所述图案化聚合物层暴露的所述导电材料的暴露部分，以从所述半导体衬底释放所述导电图案的一部分，以形成所述微线圈的面外绕组，将第二导电材料沉积在暴露的部分导电材料，并去除牺牲层。图案化导电材料可以包括微线圈的绕组部分，电容器的重叠电极部分和用于电容器电极的支撑部分。

9. 发明申请

US20060128057A1 Xerographic micro-assembler 有权
标题翻译：静电复印机
公开(公告)号：US20060128057A1
公开(公告)日：2006-06-15
申请号：US11011652
申请日：2004-12-14
申请人： Jeng Lu , Eugene Chow
发明人： Jeng Lu , Eugene Chow
IPC分类号： H01L21/50 , H01L21/30 , B23P21/00
CPC分类号： H01L25/50 , H01L21/67271 , H01L21/67282 , H01L21/67294 , H01L24/95 , H01L2224/95085 , H01L2224/95144 , H01L2224/95145 , H01L2924/14 , H01L2924/1461 , Y10T29/4913 , Y10T29/49133 , Y10T29/53004 , Y10T29/5313 , Y10T29/53174 , Y10T29/53178 , Y10T29/53278 , H01L2924/00
摘要： Xerographic micro-assembler systems and methods are disclosed. The systems and methods involve manipulating charge-encoded micro-objects. The charge encoding identifies each micro-object and specifies its orientation for sorting. The micro-objects are sorted in a sorting unit so that they have defined positions and orientations. The sorting unit has the capability of electrostatically and magnetically manipulating the micro-objects based on their select charge encoding. The sorted micro-objects are provided to an image transfer unit. The image transfer unit is adapted to receive the sorted micro-objects, maintain them in their sorted order and orientation, and deliver them to a substrate. Maintaining the sorted order as the micro-objects are delivered to the substrate may be accomplished through the use of an electrostatic image, as is done in xerography. The substrate with the micro-objects is further processed to interconnect the micro-objects—through electrical wiring, for example—to form the final micro-assembly.
摘要翻译：公开了静电印刷微组装系统和方法。系统和方法涉及操纵电荷编码的微物体。电荷编码识别每个微物体并指定其排列方向。微物体在分类单元中排序，使得它们具有定义的位置和取向。分选单元具有基于其选择电荷编码的静电和磁性操纵微物体的能力。分类的微物体被提供给图像传送单元。图像传送单元适于接收分类的微物体，将它们保持在排列顺序和方位，并将其传送到基底。将排序的顺序作为微物体传送到基底可以通过使用静电图像来实现，如在静电复印中所做的那样。具有微物体的衬底被进一步处理以使例如微通孔电线互连，以形成最终的微组件。

10. 发明申请

US20060087335A1 Curved spring structure with elongated section located under cantilevered section 有权
标题翻译：弯曲弹簧结构，细长部分位于悬臂部分下方
公开(公告)号：US20060087335A1
公开(公告)日：2006-04-27
申请号：US10971467
申请日：2004-10-21
申请人： Thomas Hantschel , Eugene Chow
发明人： Thomas Hantschel , Eugene Chow
IPC分类号： G01R31/02
CPC分类号： H01G5/18 , G01R1/06738
摘要： A curved spring structure includes a base section extending parallel to the substrate surface, a curved cantilever section bent away from the substrate surface, and an elongated section extending from the base section along the substrate surface under the cantilevered section. The spring structure includes a spring finger formed from a self-bending material film (e.g., stress-engineered metal, bimorph/bimetallic) that is patterned and released. A cladding layer is then electroplated and/or electroless plated onto the spring finger for strength. The elongated section is formed from plating material deposited simultaneously with cladding layers. To promote the formation of the elongated section, a cementation layer is provided under the spring finger to facilitate electroplating, or the substrate surface is pre-treated to facilitate electroless plating.
摘要翻译：弯曲弹簧结构包括平行于基板表面延伸的基部部分，弯曲的远离基板表面的弯曲悬臂部分，以及从基部沿着悬臂部分下方的基板表面延伸的细长部分。弹簧结构包括由图案化和释放的自弯曲材料膜（例如，应力工程金属，双晶型/双金属）形成的弹簧指状物。然后将包覆层电镀和/或无电镀在弹簧手指上用于强度。细长部分由与包覆层同时沉积的电镀材料形成。为了促进细长部分的形成，在弹簧指状物下方设置有胶结层以促进电镀，或者基板表面被预处理以便于化学镀。

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