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1. 发明申请

US20070221611A1 Method of manufacturing fine features for thin film transistors 有权
标题翻译：制造薄膜晶体管精细特征的方法
公开(公告)号：US20070221611A1
公开(公告)日：2007-09-27
申请号：US11388731
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
IPC分类号： H01B13/00 , C23F1/00
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292
摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
摘要翻译：一种在晶体管上制造诸如小栅电极的精细特征的工艺。该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

2. 发明申请

US20070221610A1 Method using monolayer etch masks in combination with printed masks 失效
标题翻译：使用单层蚀刻掩模与印刷掩模组合的方法
公开(公告)号：US20070221610A1
公开(公告)日：2007-09-27
申请号：US11388718
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Jeng Lu , Ana Arias
IPC分类号： H01B13/00 , B44C1/22
CPC分类号： H01L21/302 , H01L21/0271 , H01L21/0273 , H01L27/124 , H01L27/1288 , H01L27/1292 , H01L29/66765
摘要： A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.
摘要翻译：将薄膜图案尺寸小于印刷像素掩模尺寸的方法。印刷的掩模沉积在基底上的薄膜上。第二掩模层选择性地沉积在膜上，而不是印刷在掩模上。然后将第三掩模印刷到基底上以对第二掩模的一部分进行图案化。然后使用某些溶剂去除印刷的掩模，而不是薄膜上的掩模层。然后将掩模层与蚀刻结合在薄膜上形成图案。形成在薄膜中的特征小于印刷掩模的最小尺寸。涂覆的掩模层可以是选择性地结合薄膜的自组装单层或其它材料。

3. 发明申请

US20070046705A1 Detecting defective ejector in digital lithography system 失效
标题翻译：在数字光刻系统中检测有缺陷的喷射器
公开(公告)号：US20070046705A1
公开(公告)日：2007-03-01
申请号：US11218416
申请日：2005-09-01
申请人： William Wong , Steven Ready , Ana Arias
发明人： William Wong , Steven Ready , Ana Arias
IPC分类号： B41J29/38
CPC分类号： B41J29/393
摘要： A digital lithography system prints a large-area electronic device by dividing the overall device printing process into a series of discrete feature printing sub-processes, where each feature printing sub-process involves printing both a predetermined portion (feature) of the device in a designated substrate area, and an associated test pattern in a designated test area that is remote from the feature. At the end of each feature printing sub-process, the test pattern is analyzed, e.g., using a camera and associated imaging system, to verify that the test pattern has been successfully printed. A primary ejector is used until an unsuccessfully printed test pattern is detected, at which time a secondary (reserve) ejector replaces the primary ejector and reprints the feature associated with the defective test pattern. When multiple printheads are used in parallel, analysis of the test pattern is used to efficiently identify the location of a defective ejector.
摘要翻译：数字光刻系统通过将整个设备打印过程划分成一系列离散特征打印子过程来打印大面积电子设备，其中每个特征打印子过程涉及将设备的预定部分（特征）打印在一个指定的基板区域以及远离该特征的指定测试区域中的关联测试图案。在每个特征打印子过程结束时，分析测试图案，例如使用相机和相关联的成像系统来验证测试图案是否已被成功打印。使用初级喷射器，直到检测到未成功打印的测试图案，此时次要（预留）喷射器取代主喷射器并重印与缺陷测试图案相关的特征。当并行使用多个打印头时，使用测试图案的分析来有效地识别有缺陷的喷射器的位置。

4. 发明申请

US20070020883A1 Patterned structures fabricated by printing mask over lift-off pattern 有权
标题翻译：通过在剥离模式上印刷掩模制造的图案化结构
公开(公告)号：US20070020883A1
公开(公告)日：2007-01-25
申请号：US11184304
申请日：2005-07-18
申请人： Ana Arias , Rene Lujan , William Wong
发明人： Ana Arias , Rene Lujan , William Wong
IPC分类号： H01L21/30
CPC分类号： H01L21/027 , H01L21/0272 , H01L27/1292 , H01L29/66765 , H01L51/0016
摘要： A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e.g., by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.
摘要翻译：限定间隙或通孔的图案化集成电路结构仅通过数字印刷和批量处理来制造。牺牲剥离图案印刷或以其它方式形成在衬底上，然后被覆盖层覆盖。然后形成掩模，例如通过印刷覆盖对应于所需图案化结构的橡皮布层的区域并与剥离图案重叠的蜡图案。然后例如通过湿蚀刻除去覆盖层的暴露部分。然后使用剥离过程去除印刷的掩模和剥离图案，剥离过程也去除在剥离图案上形成的覆盖层的任何剩余部分。薄膜晶体管包括通过形成通过使用栅极结构作为掩模的背景曝光工艺曝光和显影的光致抗蚀剂剥离图案而与底层栅极结构自对准的图案化源极/漏极结构。

5. 发明申请

US20060131563A1 Phase-separated composite films and methods of preparing the same 有权
标题翻译：相分离复合膜及其制备方法
公开(公告)号：US20060131563A1
公开(公告)日：2006-06-22
申请号：US11015795
申请日：2004-12-20
申请人： Alberto Salleo , Ana Arias , William Wong
发明人： Alberto Salleo , Ana Arias , William Wong
IPC分类号： H01L51/00
CPC分类号： B82Y30/00 , H01L27/28 , H01L51/0004 , H01L51/0015
摘要： Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films.
摘要翻译：提供由在图案化衬底上相分离的半导体和绝缘材料的共混物形成的复合膜。相分离在衬底上提供隔离和封装的半导体区域。还提供了制备和使用这种复合膜的方法以及包括这种复合膜的装置。

6. 发明授权

US07749916B2 Additive printed mask process and structures produced thereby 有权
标题翻译：添加印刷掩模工艺和由此生产的结构
公开(公告)号：US07749916B2
公开(公告)日：2010-07-06
申请号：US12046242
申请日：2008-03-11
申请人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
发明人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
IPC分类号： H01L21/31
CPC分类号： G02F1/133512 , B41M3/003 , B41M3/006 , G02F1/133516 , G03F7/2018 , Y10S438/942
摘要： A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
摘要翻译：数字光刻工艺首先沉积由印刷图案掩模特征组成的掩模层。印刷图案掩模特征限定了可以沉积目标材料的间隙，优选通过数字光刻工艺。如果需要，目标材料被固化或硬化成目标特征。然后选择性地去除掩模层。剩余的目标特征然后可以用作曝光或蚀刻掩模，诸如流体容纳元件的物理结构等。可以在实现数字光刻的优点的同时获得精细特征宽度，更小的打印图案化掩模特征的最小宽度制造过程。

7. 发明申请

US20070172969A1 Additive printed mask process and structures produced thereby 有权
标题翻译：添加印刷掩模工艺和由此生产的结构
公开(公告)号：US20070172969A1
公开(公告)日：2007-07-26
申请号：US10536102
申请日：2006-01-20
申请人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
发明人： William Wong , Scott Limb , Michael Chabinyc , Beverly Russo , Rene Lujan
IPC分类号： H01L21/00
CPC分类号： G02F1/133512 , B41M3/003 , B41M3/006 , G02F1/133516 , G03F7/2018 , Y10S438/942
摘要： A digital lithographic process first deposits a mask layer comprised of print patterned mask features. The print patterned mask features define gaps into which a target material may be deposited, preferably through a digital lithographic process. The target material is cured or hardened, if necessary, into target features. The mask layer is then selectively removed. The remaining target features may then be used as exposure or etch masks, physical structures such as fluid containment elements, etc. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
摘要翻译：数字光刻工艺首先沉积由印刷图案掩模特征组成的掩模层。印刷图案掩模特征限定了可以沉积目标材料的间隙，优选通过数字光刻工艺。如果需要，目标材料被固化或硬化成目标特征。然后选择性地去除掩模层。剩余的目标特征可以用作曝光或蚀刻掩模，诸如流体容纳元件的物理结构等。可以在实现数字光刻的优点的同时获得精细特征宽度，打印图案化掩模特征的最小宽度更窄制造过程。

8. 发明申请

US20070172774A1 Process for forming a feature by undercutting a printed mask 有权
标题翻译：通过底切印刷掩模形成特征的方法
公开(公告)号：US20070172774A1
公开(公告)日：2007-07-26
申请号：US11336365
申请日：2006-01-20
申请人： Scott Limb , William Wong , Steven Ready , Michael Chabinyc
发明人： Scott Limb , William Wong , Steven Ready , Michael Chabinyc
IPC分类号： G03F7/26
CPC分类号： G03F7/0007 , G02F1/133516 , G03F7/2018
摘要： A print patterned mask is formed a digital lithographic process on the surface of a photoresist or similar material layer. The print patterned mask is then used as a development or etching mask, and the underlying layer overdeveloped or overetched to undercut the print patterned mask. The mask may be removed and the underlying structure used an etch mask or as a final structure. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
摘要翻译：打印图案化掩模在光致抗蚀剂或类似材料层的表面上形成数字平版印刷工艺。然后将印刷图案化掩模用作显影或蚀刻掩模，并且底层被发展或过蚀刻以削去印刷图案掩模。可以去除掩模，并且底层结构使用蚀刻掩模或作为最终结构。可以在实现数字光刻在制造过程中的益处的同时获得细微的特征宽度，使印刷图案化掩模特征的最小宽度更窄。

9. 发明授权

US07498119B2 Process for forming a feature by undercutting a printed mask 有权
标题翻译：通过底切印刷掩模形成特征的方法
公开(公告)号：US07498119B2
公开(公告)日：2009-03-03
申请号：US11336365
申请日：2006-01-20
申请人： Scott Limb , William Wong , Steven Ready , Michael Chabinyc
发明人： Scott Limb , William Wong , Steven Ready , Michael Chabinyc
IPC分类号： G03F7/20 , G03F7/26 , G03F7/38
CPC分类号： G03F7/0007 , G02F1/133516 , G03F7/2018
摘要： A print patterned mask is formed a digital lithographic process on the surface of a photoresist or similar material layer. The print patterned mask is then used as a development or etching mask, and the underlying layer overdeveloped or overetched to undercut the print patterned mask. The mask may be removed and the underlying structure used an etch mask or as a final structure. Fine feature widths, narrower the minimum width of the print patterned mask features, may be obtained while realizing the benefits of digital lithography in the manufacturing process.
摘要翻译：打印图案化掩模在光致抗蚀剂或类似材料层的表面上形成数字平版印刷工艺。然后将印刷图案化掩模用作显影或蚀刻掩模，并且底层被发展或过蚀刻以削去印刷图案掩模。可以去除掩模，并且底层结构使用蚀刻掩模或作为最终结构。可以在实现数字光刻在制造过程中的益处的同时获得细微的特征宽度，使印刷图案化掩模特征的最小宽度更窄。

10. 发明申请

US20060063369A1 Sub-resolution gaps generated by controlled over-etching 有权
标题翻译：通过控制过蚀刻产生的子分辨率间隙
公开(公告)号：US20060063369A1
公开(公告)日：2006-03-23
申请号：US10943624
申请日：2004-09-17
申请人： JengPing Lu , Jackson Ho , Chinwen Shih , Michael Chabinyc , William Wong
发明人： JengPing Lu , Jackson Ho , Chinwen Shih , Michael Chabinyc , William Wong
IPC分类号： H01L21/4763 , H01L21/302
CPC分类号： H01L21/76838 , B82Y30/00 , H01L21/28506 , H01L27/124
摘要： Controlled overetching is utilized to produce metal patterns having gaps that are smaller than the resolution limits of the feature patterning (e.g., photolithography) process utilized to produce the metal patterns. A first metal layer is formed and masked, and exposed regions are etched away. The etching process is allowed to continue in a controlled manner to produced a desired amount of over-etching (i.e., undercutting the mask) such that an edge of the first metal layer is offset from an edge of the mask by a predetermined gap distance. A second metal layer is then deposited such that an edge of the second metal layer is spaced from the first metal layer by the predetermined gap distance. The metal gap is used to define, for example, transistor channel lengths, thereby facilitating the production of transistors having channel lengths defined by etching process control that are smaller than the process resolution limits.
摘要翻译：控制过蚀刻用于产生具有小于用于产生金属图案的特征图案化（例如，光刻）工艺的分辨率限制的间隙的金属图案。第一金属层被形成并被掩蔽，并且暴露的区域被蚀刻掉。允许蚀刻处理以受控的方式继续，以产生期望量的过蚀刻（即，底切掩模），使得第一金属层的边缘以预定的间隙距离偏离掩模的边缘。然后沉积第二金属层，使得第二金属层的边缘与第一金属层隔开预定的间隙距离。金属间隙用于限定例如晶体管沟道长度，由此有助于生产具有小于工艺分辨率极限的蚀刻工艺控制定义的沟道长度的晶体管。

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