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    • 4. 发明授权
    • Complementary depletion switch body stack off-chip driver
    • 互补耗尽开关体堆栈片外驱动
    • US06177818B1
    • 2001-01-23
    • US09303508
    • 1999-04-30
    • Claude L. BertinAnthony R. BonaccioHoward L. KalterThomas M. MaffittJack A. MandelmanWilliam R. Tonti
    • Claude L. BertinAnthony R. BonaccioHoward L. KalterThomas M. MaffittJack A. MandelmanWilliam R. Tonti
    • H03B2100
    • H03K19/09482H03K19/00361H03K19/018521
    • An off-chip driver circuit including an enhancement PFET, a depletion PFET, a depletion NFET and an enhancement NFET connected in series. The large enhancement PFET and large enhancement NFET turn off the OCD in tri-state and to turn off the unused half of the OCD to prevent overlap current when driving a ‘0’ or a ‘1’. A first gate signal is applied to the gate of the enhancement PFET and a second gate signal is applied to the enhancement NFET. A fixed voltage is connected to the gate of the depletion NFET and ground to gate of the depletion PFET. An output signal is obtained from a node between the depletion PFET and depletion NFET devices. In another embodiment, a reflection/overshoot sensor 60 is added. The output of sensor is connected to the body of a depletion PFET and an NFET. The feedback from sensor is such that the threshold voltage of the depletion devices are made more positive if the sensor detects that the output is being over-driven. A more positive threshold voltage will reduce the driver's IDS, but leaves the device in the linear mode.
    • 包括增强型PFET,耗尽型PFET,耗尽型NFET和增强型NFET的片外驱动电路。 大增强型PFET和大增强型NFET在三态关闭OCD并关闭OCD的未使用的一半以防止在驱动“0”或“1”时重叠电流。 第一栅极信号被施加到增强PFET的栅极,并且第二栅极信号被施加到增强NFET。 固定电压连接到耗尽型NFET的栅极,并连接到耗尽PFET的栅极。 从耗尽PFET和耗尽NFET器件之间的节点获得输出信号。 在另一个实施例中,添加了反射/过冲传感器60。 传感器的输出连接到耗尽PFET和NFET的主体。 来自传感器的反馈使得如果传感器检测到输出被过驱动,则耗尽装置的阈值电压变得更为正。 更正的阈值电压将减少驾驶员的IDS,但使设备处于线性模式。
    • 6. 发明授权
    • Structures for wafer level test and burn-in
    • 晶圆级测试和老化的结构
    • US06233184B1
    • 2001-05-15
    • US09191954
    • 1998-11-13
    • John E. BarthClaude L. BertinJeffrey H. DreibelbisWayne F. EllisWayne J. HowellErik L. HedbergHoward L. KalterWilliam R. TontiDonald L. Wheater
    • John E. BarthClaude L. BertinJeffrey H. DreibelbisWayne F. EllisWayne J. HowellErik L. HedbergHoward L. KalterWilliam R. TontiDonald L. Wheater
    • G11C2900
    • G01R31/2855G01R31/2806G01R31/2831G01R31/31905H01L2224/05624H01L2224/13H01L2224/45144H01L2224/45147H01L2924/00014
    • Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
    • 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接,并且每个测试引擎可以连接到多个芯片,例如晶片上的行或一列芯片。 因此,仍然提供必须连接用于测试的晶片的焊盘数量,同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余,以便在老化完成后可以修复故障的芯片。 此外,可编程测试引擎可以对其代码进行更改,因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号,为阵列提供更高的有效电压,从而降低老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开,因此短路芯片可以断开。 优选地,膜在测试之后保留在晶片上,老化和切割以提供芯片级封装。 因此,避免了TCE匹配材料(例如玻璃陶瓷接触器)用于晶片老化的非常高的成本,同时提供超出测试和包装封装的优点。
    • 7. 发明授权
    • Structures for wafer level test and burn-in
    • 晶圆级测试和老化的结构
    • US06426904B2
    • 2002-07-30
    • US09803500
    • 2001-03-09
    • John E. BarthClaude L. BertinJeffrey H. DreibelbisWayne F. EllisWayne J. HowellErik L. HedbergHoward L. KalterWilliam R. TontiDonald L. Wheater
    • John E. BarthClaude L. BertinJeffrey H. DreibelbisWayne F. EllisWayne J. HowellErik L. HedbergHoward L. KalterWilliam R. TontiDonald L. Wheater
    • G11C2900
    • G01R31/2855G01R31/2806G01R31/2831G01R31/31905H01L2224/05624H01L2224/13H01L2224/45144H01L2224/45147H01L2924/00014
    • Wafer test and burn-in is accomplished with state machine or programmable test engines located on the wafer being tested. Each test engine requires less than 10 connections and each test engine can be connected to a plurality of chips, such as a row or a column of chips on the wafer. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. The test engines also permit on-wafer allocation of redundancy in parallel so that failing chips can be repaired after burn-in is complete. In addition, the programmable test engines can have their code altered so test programs can be modified to account for new information after the wafer has been fabricated. The test engines are used during burn-in to provide high frequency write signals to DRAM arrays that provide a higher effective voltage to the arrays, lowering the time required for burn-in. Connections to the wafer and between test engines and chips are provided along a membrane attached to the wafer. Membrane connectors can be formed or opened after the membrane is connected to the wafer so shorted chips can be disconnected. Preferably the membrane remains on the wafer after test, burn-in and dicing to provide a chip scale package. Thus, the very high cost of TCE matched materials, such as glass ceramic contactors, for wafer burn-in is avoided while providing benefit beyond test and burn-in for packaging.
    • 晶圆测试和老化是通过位于被测晶片上的状态机或可编程测试引擎完成的。 每个测试引擎需要少于10个连接,并且每个测试引擎可以连接到多个芯片,例如晶片上的行或一列芯片。 因此,仍然提供必须连接用于测试的晶片的焊盘数量,同时还提供大量的并行测试。 测试引擎还允许并行的片上分配冗余,以便在老化完成后可以修复故障的芯片。 此外,可编程测试引擎可以对其代码进行更改,因此可以修改测试程序以在晶圆制造之后考虑新的信息。 在老化期间使用测试引擎向DRAM阵列提供高频写入信号,为阵列提供更高的有效电压,从而降低了老化所需的时间。 沿着连接到晶片的膜提供与晶片和测试引擎与芯片之间的连接。 膜连接器可以在膜连接到晶片之后形成或打开,因此短路芯片可以断开。 优选地,膜在测试之后保留在晶片上,老化和切割以提供芯片级封装。 因此,避免了TCE匹配材料(例如玻璃陶瓷接触器)用于晶片老化的非常高的成本,同时提供超出测试和包装封装的优点。
    • 9. 发明授权
    • Method and apparatus for providing self-terminating signal lines
    • 用于提供自终端信号线的方法和装置
    • US06294942B2
    • 2001-09-25
    • US09264930
    • 1999-03-09
    • Claude L. BertinAnthony R. BonaccioHoward KalterWilliam R. Tonti
    • Claude L. BertinAnthony R. BonaccioHoward KalterWilliam R. Tonti
    • H03K508
    • H04L25/0278H04L25/0292
    • A self-terminating module is provided that at least partially terminates a signal line when the self-terminating module is coupled thereto. The self-terminating module comprises an internal non-self-terminating module directly coupled to an internal termination circuit. Preferably an active internal termination circuit is employed. A pass circuit may be coupled between the internal termination circuit and the internal non-self-terminating module so as to pass a received signal therebetween with fewer reflected signal contributions. When a pass circuit is employed, a delay circuit responsive to a trigger signal controls signal transfer between the internal termination circuit and the internal non-self-terminating module. One or more self-terminating modules may be coupled to a signal line and the termination impedance of each module is selected to provide adequate signal line termination without significantly loading the signal line when one or more of the self-terminating modules are coupled thereto.
    • 提供了自终端模块,当自终端模块耦合到其时,至少部分地终止信号线。 自终端模块包括直接耦合到内部终端电路的内部非自终端模块。 优选使用有源内部终端电路。 通路电路可以耦合在内部终端电路和内部非自终端模块之间,以便以较少的反射信号贡献传递其间的接收信号。 当采用通路电路时,响应于触发信号的延迟电路控制内部终端电路和内部非自终端模块之间的信号传输。 一个或多个自终端模块可以耦合到信号线,并且当一个或多个自终端模块耦合到其上时,选择每个模块的终端阻抗以提供足够的信号线终止而不显着加载信号线。