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1. 发明授权

US4982360A Memory subsystem 失效
标题翻译：内存子系统
公开(公告)号：US4982360A
公开(公告)日：1991-01-01
申请号：US534927
申请日：1983-09-22
申请人： William N. Johnson , Le T. Nguyen , Richard L. Sites , Stanley A. Lackey
发明人： William N. Johnson , Le T. Nguyen , Richard L. Sites , Stanley A. Lackey
IPC分类号： G11C17/00 , G06F9/445 , G06F12/06 , G11C7/22 , G11C8/18 , G11C16/02 , G11C29/28
CPC分类号： G06F8/66 , G06F12/0638 , G06F9/328 , G11C29/28 , G11C7/22 , G11C8/18
摘要： A memory subsystem including a read-only memory (ROM), a random access read/write memory (RAM) and a selection system for selecting the output of one of the memories for use by downstream circuitry. The selection of the output is based on input address signals so that the contents of the RAM can substitute for the contents of selected locations in the ROM. If a substitution is to be made, an entry is made in a content addressable memory, which stores addresses for which the RAM output is to be substituted for ROM output. A test system is provided to verify the contents of the content addressable memory.
摘要翻译：包括只读存储器（ROM），随机存取读/写存储器（RAM）和选择系统的存储器子系统，用于选择一个存储器的输出以供下游电路使用。输出的选择基于输入地址信号，使得RAM的内容可以替代ROM中所选位置的内容。如果要进行替换，则在内容可寻址存储器中作出条目，该存储器存储RAM输出被替换为ROM输出的地址。提供测试系统来验证内容可寻址存储器的内容。

2. 发明授权

US5860158A Cache control unit with a cache request transaction-oriented protocol 失效
标题翻译：缓存控制单元具有缓存请求面向事务的协议
公开(公告)号：US5860158A
公开(公告)日：1999-01-12
申请号：US751149
申请日：1996-11-15
申请人： Yet-Ping Pai , Le T. Nguyen
发明人： Yet-Ping Pai , Le T. Nguyen
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/084
摘要： A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.
摘要翻译：高速缓存控制单元和控制高速缓存的方法。缓存耦合到高速缓存访问设备。从设备接收到第一个缓存请求。请求识别信息被分配给第一高速缓存请求并提供给请求设备。第一个缓存请求可能开始被处理。从高速缓存访问设备接收第二高速缓存请求。第二缓存请求被分配给第一高速缓存请求并提供给请求设备。第一个和第二个缓存请求终于被完全服务了。

3. 发明授权

US5581562A Integrated circuit device implemented using a plurality of partially defective integrated circuit chips 失效
标题翻译：使用多个部分缺陷的集成电路芯片实现的集成电路器件
公开(公告)号：US5581562A
公开(公告)日：1996-12-03
申请号：US325946
申请日：1994-10-19
申请人： Chong M. Lin , Wai-Yan Ho , Le T. Nguyen
发明人： Chong M. Lin , Wai-Yan Ho , Le T. Nguyen
IPC分类号： G01R31/28 , G06F11/26 , G06F17/50 , G06F11/00
CPC分类号： G06F17/5027
摘要： An integrated circuit (IC) device implemented according to an architectural design that specifies that the IC device is required to have one functional module, to perform a first function, connected to another functional module, to perform a second function. The IC device includes a first IC chip having a plurality of first functional modules implemented thereon. Some of the first functional modules are defective and others of the first functional modules are non-defective. At least one of the non-defective first functional modules is operable to perform the first function. The IC device also includes a second IC chip having a plurality of second functional modules implemented thereon. Some of the second functional modules are defective and others of the second functional modules are non-defective. At least one of the non-defective second functional modules is operable to perform the second function. The IC device further includes a bus, a first tri-state gate to electrically connect the non-defective first functional module to the bus, and the second tri-state gate to electrically connect the non-defective second functional modules to the bus.
摘要翻译：根据建筑设计实现的集成电路（IC）装置，其指定IC器件需要具有一个功能模块，以执行连接到另一功能模块的第一功能，以执行第二功能。 IC器件包括具有多个第一功能模块的第一IC芯片。第一功能模块中的一些是有缺陷的，第一功能模块中的其它模块是无缺陷的。至少一个无缺陷的第一功能模块可操作以执行第一功能。 IC器件还包括具有在其上实现的多个第二功能模块的第二IC芯片。第二功能模块中的一些是有缺陷的，第二功能模块中的其它功能模块是无缺陷的。至少一个无缺陷的第二功能模块可操作以执行第二功能。 IC器件还包括总线，将无缺陷第一功能模块电连接到总线的第一三态门和第二三态门，以将无缺陷的第二功能模块电连接到总线。

4. 发明授权

US5497499A Superscalar risc instruction scheduling 失效
标题翻译：超标量risc指令调度
公开(公告)号：US5497499A
公开(公告)日：1996-03-05
申请号：US219425
申请日：1994-03-29
申请人： Sanjiv Garg , Kevin R. Iadonato , Le T. Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin R. Iadonato , Le T. Nguyen , Johannes Wang
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路，用于确定指令之间的数据依赖性。标签分配电路根据由数据依赖性检查电路确定的数据依赖性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

5. 发明授权

US5493687A RISC microprocessor architecture implementing multiple typed register sets 失效
公开(公告)号：US5493687A
公开(公告)日：1996-02-20
申请号：US726773
申请日：1991-07-08
申请人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

6. 发明授权

US5943250A Parallel multiplier that supports multiple numbers with different bit lengths 失效
标题翻译：支持多个不同位长数字的并行乘法器
公开(公告)号：US5943250A
公开(公告)日：1999-08-24
申请号：US734277
申请日：1996-10-21
申请人： Chang Soo Kim , Le T. Nguyen , Roney S. Wong
发明人： Chang Soo Kim , Le T. Nguyen , Roney S. Wong
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F2207/3828
摘要： A parallel multiplier for multiplying a multiplicand and multiplier with large bit lengths as well as simultaneously multiplying several multiplicands and multipliers with smaller bit lengths is disclosed. The parallel multiplier receives an N-bit multiplicand operand, an M-bit multiplier operand, and a data length signal. The parallel multiplier calculates an N+M bit product of an N-bit multiplicand from the multiplicand operand and an M-bit multiplier from the multiplier operand when the data length signal selects a first bit length. Furthermore, the parallel multiplier simultaneously calculates an (N+M)/2 bit first product of an N/2 bit first multiplicand from the multiplicand operand and an M/2 bit first multiplier from the multiplier operand, and an (N+M)/2 bit second product of an N/2 bit second multiplicand from the multiplicand operand and an M/2 bit second multiplier from the multiplier operand when the data length signal selects a second bit length.
摘要翻译：公开了一种并行乘法器，用于将乘法器和乘法器与大位长度相乘，以及同时乘以具有较小位长度的多个乘法器和乘法器。并行乘法器接收N位被乘数操作数，M位乘法器操作数和数据长度信号。当数据长度信号选择第一位长度时，并行乘法器计算来自乘法器操作数的N位被乘数的N + M位乘积和来自乘法器操作数的M位乘法器。此外，并行乘法器同时计算来自乘法器操作数的N / 2位第一被乘数的第（N + M）/ 2位第一乘积和来自乘法器操作数的M / 2位第一乘法器，并且（N + M）当从数据长度信号选择第二位长度时，来自乘法器操作数的N / 2位第二被乘数的2位第二乘积和来自乘法器操作数的M / 2位第二乘法器。

7. 发明授权

US5560035A RISC microprocessor architecture implementing multiple typed register sets 失效
公开(公告)号：US5560035A
公开(公告)日：1996-09-24
申请号：US465239
申请日：1995-06-05
申请人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

8. 发明授权

US5371684A Semiconductor floor plan for a register renaming circuit 失效
标题翻译：注册重命名电路的半导体平面图
公开(公告)号：US5371684A
公开(公告)日：1994-12-06
申请号：US860718
申请日：1992-03-31
申请人： Kevin R. Iadonato , Le T. Nguyen
发明人： Kevin R. Iadonato , Le T. Nguyen
IPC分类号： G06F5/00 , G06F7/00 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/40 , G06F15/00 , G06F15/76 , G06F17/00 , G06F17/50 , G06F19/00 , H01L21/82 , H01L27/00 , G06F15/60
CPC分类号： G06F9/30141 , G06F17/5068 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A semiconductor floorplan layout for integrating a Data Dependency Checker (DDC) circuit and a Tag Assignment Logic (TAL) of a Register Renaming Circuit (RRC) circuit to conserve valuable semiconductor realestate. Floorplans of present invention contemplate laying out the DDC and TAL in such a fashion as to reduce the distance signals must travel between the DDC and TAL, as well as the distance signals must travel between the TAL and RPM. By rearranging selected DDC comparator rows and their associated TAL, a considerable amount of area can be conserved for performing register renaming for up to eight instructions.
摘要翻译：一种用于集成数据相关性检查器（DDC）电路和寄存器重命名电路（RRC）电路的标签分配逻辑（TAL）的半导体平面图布局，以节省有价值的半导体不动态。本发明的平面布置考虑以如下方式布置DDC和TAL，以减少在DDC和TAL之间必须行进的距离信号，以及距离信号必须在TAL和RPM之间行进。通过重新排列所选的DDC比较器行及其关联的TAL，可以节省大量的面积，以便最多执行8个指令的寄存器重命名。

9. 发明授权

US06061711A Efficient context saving and restoring in a multi-tasking computing system environment 失效
标题翻译：在多任务计算系统环境中高效的上下文保存和恢复
公开(公告)号：US06061711A
公开(公告)日：2000-05-09
申请号：US699280
申请日：1996-08-19
申请人： Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Le T. Nguyen , Jerry R. Van Aken , Alessandro Forin , Andrew R. Raffman
发明人： Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Le T. Nguyen , Jerry R. Van Aken , Alessandro Forin , Andrew R. Raffman
IPC分类号： G06F9/44 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F17/16
CPC分类号： G06F9/30087 , G06F9/30003 , G06F9/30036 , G06F9/30043 , G06F9/3009 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3887 , G06F9/461
摘要： In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program. Unnecessarily saving and loading all available processor state information can be noticeably inefficient particularly where relatively large amounts of processor state information exists. In one embodiment, a processor requests a co-processor to context switch out the currently executing program. At a predetermined appropriate point in the executing program, the co-processor responds by halting program execution and saving only the minimal amount of processor state information necessary for successful restoration of the program. The appropriate point is chosen by the application programmer at a location in the executing program that requires preserving a minimal portion of the processor information across a context switch. By saving only a minimal amount of processor information, processor time savings are accumulated across context save and restoration operations.
摘要翻译：在多任务计算系统环境中，停止一个程序并上下文切换，使得处理器可以在后续程序中上下文切换以执行。存在反映正在上下文切换的程序的状态的处理器状态信息。该处理器状态信息的存储允许成功恢复上下文切换程序。当上下文切换程序随后进行上下文切换时，加载所存储的处理器信息以准备好在先前停止执行的点成功恢复程序。尽管可以将大面积的存储器分配给处理器状态信息存储，但是只有一部分可能需要在上下文切换中被保留以成功地保存和恢复上下文切换程序。不必要地保存和加载所有可用的处理器状态信息，特别是在存在相对大量的处理器状态信息的情况下是显着的。在一个实施例中，处理器请求协处理器上下文切换当前执行的程序。在执行程序中的预定的适当点处，协处理器通过停止程序执行并且仅节省成功恢复程序所需的最小量的处理器状态信息来进行响应。应用程序员在执行程序中需要在上下文切换中保留处理器信息的最小部分的位置来选择适当的点。通过仅节省最少量的处理器信息，可以在上下文保存和恢复操作中累积处理器时间节省。

10. 发明授权

US5539911A High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US5539911A
公开(公告)日：1996-07-23
申请号：US817810
申请日：1992-01-08
申请人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F13/00
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统获取和存储程序指令集。每个指令集包括具有指定的顺序程序顺序（按顺序）的多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令集并且调度用于由功能单元执行无序执行的指令。寄存器文件包括一组临时数据寄存器，由指令执行控制单元用来接收由功能单元产生的数据结果。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

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