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1. 发明授权

US5922066A Multifunction data aligner in wide data width processor 失效
标题翻译：多功能数据对齐器在宽数据宽度处理器
公开(公告)号：US5922066A
公开(公告)日：1999-07-13
申请号：US805392
申请日：1997-02-24
申请人： Seongrai Cho , Heonchul Park , Seungyoon Peter Song
发明人： Seongrai Cho , Heonchul Park , Seungyoon Peter Song
IPC分类号： G06F9/38 , G06F5/01 , G06F11/26
CPC分类号： G06F5/015 , G06F9/30032 , G06F9/30036 , G06F9/345
摘要： A wide data width processor has an execution unit including an aligner that aligns data for load/store instructions and shifts or rotates data for arithmetic logic instructions. Use of the same circuitry and execution unit for these different types of instructions reduces overall circuit size because alignment circuitry need not be repeated, once in a load/store unit and once in an arithmetic logic unit.
摘要翻译：宽数据宽度处理器具有执行单元，该执行单元包括对准器，其对准用于加载/存储指令的数据，并移位或旋转用于算术逻辑指令的数据。对于这些不同类型的指令使用相同的电路和执行单元减少了总体电路尺寸，因为对准电路不需要重复，一次在加载/存储单元中，并且一次在算术逻辑单元中。

2. 发明授权

US07761688B1 Multiple thread in-order issue in-order completion DSP and micro-controller 有权
标题翻译：多线程按顺序发送顺序完成DSP和微控制器
公开(公告)号：US07761688B1
公开(公告)日：2010-07-20
申请号：US11899557
申请日：2007-09-06
申请人： Heonchul Park
发明人： Heonchul Park
IPC分类号： G06F9/00
CPC分类号： G06F9/3867 , G06F9/3851
摘要： An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage. The various stages are provided a thread ID such that alternating stages use a first thread ID, and the other stages use a second thread ID. Each stage which requires access to thread ID specific context information uses the thread ID to specify this context information.
摘要翻译：按顺序发行的顺序完成微控制器包括流水线核心，其连续地包括获取地址级，程序访问级，解码级，第一执行级，第二执行级，存储器访问级和回写阶段提供各个阶段的线程ID，使得交替阶段使用第一线程ID，并且其他阶段使用第二线程ID。需要访问线程ID特定上下文信息的每个阶段使用线程ID来指定该上下文信息。

3. 发明授权

US06865590B2 Three input variable subfield comparation for fast matching 有权
标题翻译：三输入变量子场比较快速匹配
公开(公告)号：US06865590B2
公开(公告)日：2005-03-08
申请号：US10014098
申请日：2001-12-10
申请人： Heonchul Park
发明人： Heonchul Park
IPC分类号： G06F7/02 , G06F7/50 , G06F12/08 , G06F12/10
CPC分类号： G06F7/02 , G06F12/0895 , G06F12/1027
摘要： The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the applied address operands to ensure easy access to potential carry bits. A comparator is used for each virtual page number stored in a translation look-aside buffer to quickly determine whether that virtual page number matches the applied address operand sum.
摘要翻译：利用施加的地址操作数和匹配的虚拟页数之间的关系来最小化快速数字比较所需的加法器大小。在一个实施例中，通过增加所施加的地址操作数的一部分来容纳可变大小的地址，以确保容易地访问潜在的进位位。对于存储在转换后备缓冲器中的每个虚拟页号，使用比较器来快速确定该虚拟页码是否与所应用的地址操作数和匹配。

4. 发明授权

US5978838A Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor 失效
标题翻译：不对称，单芯片双重多处理器的协调和同步
公开(公告)号：US5978838A
公开(公告)日：1999-11-02
申请号：US703434
申请日：1996-08-26
申请人： Moataz A. Mohamed , Heonchul Park , Le Trong Nguyen
发明人： Moataz A. Mohamed , Heonchul Park , Le Trong Nguyen
IPC分类号： G06F17/16 , G06F9/318 , G06F9/38 , G06F9/46 , G06F15/16
CPC分类号： G06F9/52 , G06F9/30036 , G06F9/30167 , G06F9/30192 , G06F9/3879 , G06F9/3887
摘要： An integrated multiprocessor architecture simplifies synchronization of multiple processing units. The multiple processing units constitute a general-purpose or control processor and a vector processor which has a single-instruction-multiple-data (SIMD) architecture so that multiple parallel processing units in the vector processor all complete an instruction simultaneously and do not require software synchronization. The control control processor controls the vector processor and creates a fork in a program flow by starting the vector processor. An instruction set for the control processor includes special instructions that enable the control processor to access registers of the vector processor, start or halt execution by the vector processor, and test flags written by the vector processor to indicate completion of tasks. The two processors then execute separate program threads in parallel until the control processor stops the vector processor, an exception is encountered, or the vector processor completes its program thread and enters an idle state. An instruction set for the vector processor includes special instructions that interrupt the first processor to indicate a task is complete. A register coupled to and accessible by both processors stores a state bit indicating whether the vector processor is running or idle. The control processor can synchronize the separate program threads by executing a loop which polls the state bit. When the state bit indicates the vector processor is idle, the general-purpose processor can process results from the vector processor and restart the vector processor.
摘要翻译：集成多处理器架构简化了多个处理单元的同步。多个处理单元构成具有单指令多数据（SIMD）架构的通用或控制处理器和向量处理器，使得向量处理器中的多个并行处理单元同时完成指令并且不需要软件同步控制控制处理器控制向量处理器并通过启动向量处理器在程序流中创建一个分支。用于控制处理器的指令集包括使得控制处理器能够访问向量处理器的寄存器，启动或停止由向量处理器执行的特殊指令，以及由向量处理器写入的指示完成任务的测试标志。然后，两个处理器并行执行单独的程序线程，直到控制处理器停止向量处理器，遇到异常，或者向量处理器完成其程序线程并进入空闲状态。用于向量处理器的指令集包括中断第一处理器以指示任务完成的特殊指令。耦合到两个处理器并由两个处理器访问的寄存器存储指示矢量处理器是正在运行还是空闲的状态位。控制处理器可以通过执行轮询状态位的循环来同步单独的程序线程。当状态位指示向量处理器空闲时，通用处理器可以处理来自向量处理器的结果并重新启动向量处理器。

5. 发明授权

US5838984A Single-instruction-multiple-data processing using multiple banks of vector registers 失效
标题翻译：使用多个向量寄存器组的单指令多数据处理
公开(公告)号：US5838984A
公开(公告)日：1998-11-17
申请号：US697086
申请日：1996-08-19
申请人： Le Trong Nguyen , Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Roney Sau Don Wong
发明人： Le Trong Nguyen , Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Roney Sau Don Wong
IPC分类号： G06F17/16 , G06F9/30 , G06F9/318 , G06F12/00 , G06F15/16 , G06F15/78
CPC分类号： G06F9/30025 , G06F15/8076 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189
摘要： A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector registers in the default bank, uses a register number to identify a double-size vector register including a register from the first bank and a register from the second bank, and instructions which include a bank bit and a register number to access a vector register from either bank.
摘要翻译：向量处理器包括两组向量寄存器，其中每个向量寄存器可以存储多个数据元素，一个控制寄存器具有指示默认库的字段。用于向量处理器的指令集包括使用寄存器编号来识别默认组中的向量寄存器的指令，使用寄存器编号来识别包括来自第一组的寄存器的双倍大小向量寄存器和来自第二组的寄存器，以及包括存储位和寄存器号以用于从任一个存储体访问向量寄存器的指令。

6. 发明授权

US06401194B1 Execution unit for processing a data stream independently and in parallel 失效
标题翻译：独立并行处理数据流的执行单元
公开(公告)号：US06401194B1
公开(公告)日：2002-06-04
申请号：US08790142
申请日：1997-01-28
申请人： Le Trong Nguyen , Heonchul Park , Roney S. Wong , Ted Nguyen , Edward H. Yu
发明人： Le Trong Nguyen , Heonchul Park , Roney S. Wong , Ted Nguyen , Edward H. Yu
IPC分类号： G06F9302
CPC分类号： G06F7/57 , G06F7/483 , G06F7/5443 , G06F9/30014 , G06F9/30036 , G06F2207/382 , G06F2207/3828
摘要： A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.
摘要翻译：向量处理器提供分割成更小的数据片段的数据路径，每个片段与其他片段并行处理。此外，执行单元提供较小的算术和功能单元链接在一起，以通过共享单周期操作来执行需要多个周期的更复杂的微处理器指令，从而降低了微处理器的成本和尺寸。一个实施例使用36位数据路径片处理288位数据宽度。另一个实施例使用单周期算术逻辑单元执行整数乘法和乘法和累加和浮点加法和减法运算。其他实施例支持8位，9位，16位和32位整数数据类型和32位浮点数据类型。

7. 发明授权

US5923862A Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions 失效
标题翻译：将多周期指令解码为单周期微指令并计划执行微指令的处理器
公开(公告)号：US5923862A
公开(公告)日：1999-07-13
申请号：US789574
申请日：1997-01-28
申请人： Le Trong Nguyen , Heonchul Park
发明人： Le Trong Nguyen , Heonchul Park
IPC分类号： G06F9/22 , G06F9/28 , G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3017 , G06F9/28 , G06F9/30145 , G06F9/30167 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： An instruction decoder in a processor decodes an instruction by creating a decode buffer entry that includes global fields, operand fields, and a set of micro-instructions. Each micro-instruction represent an operation that an associated execution unit can execute in a single clock cycle. A scheduler issues the micro-instructions from one or more entries to the execution units for possible parallel and out-of-order execution. Each execution unit completes an operation, typically, in one clock cycle and does not monitor instructions that may block a pipeline. The execution units do not need separate decoding for multiple stages. One global field indicates which micro-instructions are execute first. Further, micro-instructions have fields that indicate an execution sequence. The scheduler issues operations in the order indicated by the global fields and the micro-instructions. When the last operation for an instruction is completed, the instruction is retired and removed from the decode buffer.
摘要翻译：处理器中的指令解码器通过创建包括全局字段，操作数字段和一组微指令的解码缓冲器条目来解码指令。每个微指令表示相关执行单元可以在单个时钟周期内执行的操作。调度器将微指令从一个或多个条目发送到执行单元，以实现可能的并行和无序执行。每个执行单元通常在一个时钟周期内完成一个操作，并且不监视可能阻塞流水线的指令。执行单元不需要对多个阶段进行单独的解码。一个全局字段指示哪个微指令首先执行。此外，微指令具有指示执行顺序的字段。调度器按照全局字段和微指令指示的顺序发布操作。当指令的最后一个操作完成时，指令被退出并从解码缓冲器中移除。

8. 发明授权

US5889986A Instruction fetch unit including instruction buffer and secondary or branch target buffer that transfers prefetched instructions to the instruction buffer 失效
标题翻译：指令提取单元包括指令缓冲器和将预取指令传送到指令缓冲器的辅助或分支目标缓冲器
公开(公告)号：US5889986A
公开(公告)日：1999-03-30
申请号：US790028
申请日：1997-01-28
申请人： Le Trong Nguyen , Heonchul Park
发明人： Le Trong Nguyen , Heonchul Park
IPC分类号： G06F9/38 , G06F9/06
CPC分类号： G06F9/3806 , G06F9/3804
摘要： An instruction fetch unit includes a program buffer for sequential instructions being decoded and a target buffer for an instruction sequence including the target of the next branch instruction. Scan logic coupled to the program buffer scans the program buffer for branch instructions. A target for the first branch instruction is determined and a request to external memory fills the target buffer with a sequence of instructions including a target instruction before sequential decoding reaches the branch instruction. If the branch is subsequently taken, the instructions from the branch target buffer are transferred to the program buffer. The program buffer may be divided into a main and a secondary buffer that have the same size as the target buffer, and an instruction bus between the instruction fetch unit and external memory is sufficiently wide to fill the main, secondary, or target buffer in a single write operation.
摘要翻译：指令提取单元包括用于正在解码的顺序指令的程序缓冲器和用于包括下一个分支指令的目标的指令序列的目标缓冲器。耦合到程序缓冲区的扫描逻辑扫描程序缓冲区以获得分支指令。确定第一分支指令的目标，并且对外部存储器的请求在序列解码到达分支指令之前用包括目标指令的指令序列填充目标缓冲器。如果随后采取分支，则来自分支目标缓冲器的指令被传送到程序缓冲器。程序缓冲器可以被划分为与目标缓冲器具有相同大小的主缓冲器和辅助缓冲器，并且指令提取单元和外部存储器之间的指令总线足够宽以填充主缓冲器，辅助缓冲器或目标缓冲器单写操作。

9. 发明授权

US5468069A Single chip design for fast image compression 失效
标题翻译：单芯片设计，用于快速图像压缩
公开(公告)号：US5468069A
公开(公告)日：1995-11-21
申请号：US100928
申请日：1993-08-03
申请人： Viktor K. Prasanna , Cho-Li Wang , Heonchul Park
发明人： Viktor K. Prasanna , Cho-Li Wang , Heonchul Park
IPC分类号： G06T9/00 , G06K9/36 , G06K9/68
CPC分类号： G06T9/008
摘要： Video data compression techniques reduce necessary storage size and communication channel bandwidth while maintaining acceptable fidelity. Vector quantization provides better overall data compression performance by coding vectors instead of scalars. The search algorithm and VLSI architecture for implementing it is herein disclosed, and such a search algorithm is useful for real-time image processing. The architecture employs a single processing element and external memory for storing the N constant value hyperplanes used in the search, where N is the number of codevectors. The design does not perform any multiplication operation using the constant value hyperplane tree search, since the tree search method is independent of any L.sub.q metric for q between one and infinity. Memory used by the design is significantly less than memory employed in existing architecture.
摘要翻译：视频数据压缩技术在保持可接受的保真度的同时减少必要的存储大小和通信信道带宽。矢量量化通过编码矢量而不是标量来提供更好的总体数据压缩性能。这里公开了用于实现它的搜索算法和VLSI架构，并且这种搜索算法对于实时图像处理是有用的。该架构采用单个处理元件和外部存储器来存储在搜索中使用的N个恒定值超平面，其中N是代码矢量的数量。该设计不使用常数值超平面树搜索来执行任何乘法运算，因为树搜索方法独立于一个和无穷大之间的q的任何Lq度量。设计使用的内存明显小于现有架构中使用的内存。

10. 发明授权

US08396063B1 Multi-thread media access controller with per-thread MAC address 有权
标题翻译：具有每线程MAC地址的多线程媒体访问控制器
公开(公告)号：US08396063B1
公开(公告)日：2013-03-12
申请号：US11982614
申请日：2007-11-05
申请人： Narasimhan Venkatesh , Satya Rao , Heonchul Park
发明人： Narasimhan Venkatesh , Satya Rao , Heonchul Park
IPC分类号： H04L12/56
CPC分类号： H04W88/02 , H04B1/707 , H04J3/1605
摘要： A wireless signal processor for handling a plurality of wireless sessions comprises a plurality of baseband receivers, one for each session, each receiver producing a digital output, a multiplexer for multiplexing the plurality of digital outputs into a single data stream, a digital signal processor for converting the stream of multiplexed data into a media access controller format, and a media access controller for demultiplexing and framing the stream of data into a plurality of data buffers, one data buffer for each wireless session.
摘要翻译：一种用于处理多个无线会话的无线信号处理器包括多个基带接收器，每个会话一个，每个接收器产生数字输出，多路复用器，用于将多个数字输出复用为单个数据流;数字信号处理器，用于将多路复用数据流转换为媒体访问控制器格式，以及媒体访问控制器，用于将数据流解复用并成帧为多个数据缓冲器，每个无线会话的一个数据缓冲器。

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