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1. 发明授权

US5493687A RISC microprocessor architecture implementing multiple typed register sets 失效
公开(公告)号：US5493687A
公开(公告)日：1996-02-20
申请号：US726773
申请日：1991-07-08
申请人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

2. 发明授权

US5560035A RISC microprocessor architecture implementing multiple typed register sets 失效
公开(公告)号：US5560035A
公开(公告)日：1996-09-24
申请号：US465239
申请日：1995-06-05
申请人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
发明人： Sanjiv Garg , Derek J. Lentz , Le T. Nguyen , Sho L. Chen
IPC分类号： G06F9/30 , G06F9/305 , G06F9/318 , G06F9/34 , G06F9/38 , G06F9/42 , G06F9/46 , G06F9/48
CPC分类号： G06F9/30029 , G06F9/30036 , G06F9/30112 , G06F9/30116 , G06F9/3012 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/30181 , G06F9/3851
摘要： A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.

3. 发明授权

US5448705A RISC microprocessor architecture implementing fast trap and exception state 失效
标题翻译： RISC微处理器架构实现快速陷阱和异常状态
公开(公告)号：US5448705A
公开(公告)日：1995-09-05
申请号：US65063
申请日：1993-05-24
申请人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Quang Trang
发明人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Quang Trang
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/42 , G06F9/455 , G06F9/46 , G06F9/48 , G06F15/78 , G06F9/40
CPC分类号： G06F9/3865 , G06F15/7842 , G06F9/3017 , G06F9/32 , G06F9/322 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861 , G06F9/3885 , G06F9/462 , G06F9/4812
摘要： A method for use in a microprocessor to return execution to a main program after processing an interruption to the sequential processing of instructions from the main instruction stream is disclosed. The method comprises fetching instructions from a main instruction stream to a main buffer section of a prefetch buffer and executing said fetched instructions. The method also provides for handling interruptions to the processing of the main instruction stream and allowing return to the main instruction stream without requiring prefetching of instructions already fetched. Similarly, the method provides for handling interruptions of the processing of interruptions of the processing of the main instruction stream.
摘要翻译：公开了一种在处理从主指令流的指令的顺序处理中断之后在微处理器中将执行返回到主程序的方法。该方法包括从主指令流获取指令到预取缓冲器的主缓冲器部分并执行所述获取的指令。该方法还提供处理对主指令流的处理的中断，并允许返回到主指令流，而不需要预取已经获取的指令。类似地，该方法提供处理对主指令流的处理中断处理的中断。

4. 发明授权

US5539911A High-performance, superscalar-based computer system with out-of-order instruction execution 失效
标题翻译：高性能，基于超标量的计算机系统，执行无序指令
公开(公告)号：US5539911A
公开(公告)日：1996-07-23
申请号：US817810
申请日：1992-01-08
申请人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
发明人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Te-Li Lau , Sze-Shun Wang , Quang H. Trang
IPC分类号： G06F9/32 , G06F9/30 , G06F9/34 , G06F9/38 , G06F9/42 , G06F13/00
CPC分类号： G06F9/3822 , G06F9/30061 , G06F9/30072 , G06F9/30112 , G06F9/30116 , G06F9/30123 , G06F9/3013 , G06F9/30134 , G06F9/30167 , G06F9/327 , G06F9/3802 , G06F9/3804 , G06F9/3806 , G06F9/3826 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3851 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865 , G06F9/3885
摘要： A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches and stores program instruction sets. Each instruction set includes a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instruction sets and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers which are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.
摘要翻译：高性能，基于超标量的计算机系统，具有无序指令执行功能，可提高资源利用率和性能吞吐量。计算机系统获取和存储程序指令集。每个指令集包括具有指定的顺序程序顺序（按顺序）的多个固定长度指令。计算机系统包括指令执行单元，其包括寄存器文件，多个功能单元以及指令控制单元，用于检查指令集并且调度用于由功能单元执行无序执行的指令。寄存器文件包括一组临时数据寄存器，由指令执行控制单元用来接收由功能单元产生的数据结果。每个执行指令的数据结果被存储在临时数据寄存器中，直到所有先前的指令都被执行，从而按顺序退出执行的指令。

5. 发明授权

US5481685A RISC microprocessor architecture implementing fast trap and exception state 失效
标题翻译： RISC微处理器架构实现快速陷阱和异常状态
公开(公告)号：US5481685A
公开(公告)日：1996-01-02
申请号：US345333
申请日：1994-11-21
申请人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Quang Trang
发明人： Le T. Nguyen , Derek J. Lentz , Yoshiyuki Miyayama , Sanjiv Garg , Yasuaki Hagiwara , Johannes Wang , Quang Trang
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/42 , G06F9/455 , G06F9/46 , G06F9/48 , G06F15/78 , G06F9/40
CPC分类号： G06F9/3865 , G06F15/7842 , G06F9/3017 , G06F9/32 , G06F9/322 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3857 , G06F9/3861 , G06F9/3885 , G06F9/462 , G06F9/4812
摘要： Fast trap mechanism for a microprocessor, wherein a vector trap table is maintained which contains space for a plurality of instructions in each table entry. When a fast trap occurs, control is transferred directly into the table entry corresponding to the trap number. The trap handler can be located completely inside the table entry, or it can transfer control to additional handler code.
摘要翻译：一种用于微处理器的快速陷阱机制，其中维护一个向量陷阱表，其中包含每个表格条目中的多个指令的空间。当发生快速陷阱时，控制将直接传输到与陷阱号对应的表条目中。陷阱处理程序可以完全位于表条目中，也可以将控制权转移到附加的处理程序代码。

6. 发明授权

US5564117A Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units 失效
标题翻译：计算机系统包括页面打印机控制器，其包括具有图形功能单元的单芯片超标准微处理器
公开(公告)号：US5564117A
公开(公告)日：1996-10-08
申请号：US468083
申请日：1995-06-06
申请人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le T. Nguyen , Makoto Matsubayashi , Te-Li Lau
发明人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le T. Nguyen , Makoto Matsubayashi , Te-Li Lau
IPC分类号： B41J5/30 , B41J29/38 , G06F3/12 , G06F9/308 , G06F15/78 , G06K15/00 , G06K15/02 , G06T1/20 , G06F15/16
CPC分类号： G06F9/30018 , G06K15/00 , G06K15/02 , G06K2215/0002 , G06K2215/0005 , G06K2215/004 , G06K2215/0054 , G06K2215/0062 , G06K2215/0071 , G06K2215/0082
摘要： A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function, circuits of orthogonal rotator, bit/byte mirror, and pixel modification.
摘要翻译： VLSIC页面打印机控制器包括指令处理器，其响应于主计算机和打印机视频处理器，用于在指令处理器的控制下从存储器访问数据，并串行化数据以通过视频端口传送到打印机。 I / O接口将打印机控制器与连接到主机，存储设备和其他外围设备的I / O总线互连。内部存储器接口将打印机控制器连接到存储器，并且打印机视频处理器具有直接存储器访问（DMA）。数据和指令高速缓存以及指令ROM片上提供。 RISC指令处理单元作为其整体部分包括特殊功能，正交旋转器的电路，位/字节镜和像素修改。

7. 发明授权

US5497499A Superscalar risc instruction scheduling 失效
标题翻译：超标量risc指令调度
公开(公告)号：US5497499A
公开(公告)日：1996-03-05
申请号：US219425
申请日：1994-03-29
申请人： Sanjiv Garg , Kevin R. Iadonato , Le T. Nguyen , Johannes Wang
发明人： Sanjiv Garg , Kevin R. Iadonato , Le T. Nguyen , Johannes Wang
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3013 , G06F9/3824 , G06F9/3838 , G06F9/384 , G06F9/3855
摘要： A register renaming system for out-of-order execution of a set of reduced instruction set computer instructions having addressable source and destination register fields, adapted for use in a computer having an instruction execution unit with a register file accessed by read address ports and for storing instruction operands. A data dependance check circuit is included for determining data dependencies between the instructions. A tag assignment circuit generates one of more tags to specify the location of operands, based on the data dependencies determined by the data dependance check circuit. A set of register file port multiplexers select the tags generated by the tag assignment circuit and pass the tags onto the read address ports of the register file for storing execution results.
摘要翻译：一种用于无序执行一组具有可寻址源和目的寄存器字段的精简指令集计算机指令的寄存器重命名系统，适用于具有指令执行单元的计算机，该指令执行单元具有通过读地址端口访问的寄存器文件，存储指令操作数。包括数据相关性检查电路，用于确定指令之间的数据依赖性。标签分配电路根据由数据依赖性检查电路确定的数据依赖性，生成更多标签之一以指定操作数的位置。一组寄存器文件端口复用器选择标签分配电路产生的标签，并将标签传递到寄存器文件的读取地址端口，以存储执行结果。

8. 发明授权

US5860158A Cache control unit with a cache request transaction-oriented protocol 失效
标题翻译：缓存控制单元具有缓存请求面向事务的协议
公开(公告)号：US5860158A
公开(公告)日：1999-01-12
申请号：US751149
申请日：1996-11-15
申请人： Yet-Ping Pai , Le T. Nguyen
发明人： Yet-Ping Pai , Le T. Nguyen
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/084
摘要： A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.
摘要翻译：高速缓存控制单元和控制高速缓存的方法。缓存耦合到高速缓存访问设备。从设备接收到第一个缓存请求。请求识别信息被分配给第一高速缓存请求并提供给请求设备。第一个缓存请求可能开始被处理。从高速缓存访问设备接收第二高速缓存请求。第二缓存请求被分配给第一高速缓存请求并提供给请求设备。第一个和第二个缓存请求终于被完全服务了。

9. 发明授权

US5581562A Integrated circuit device implemented using a plurality of partially defective integrated circuit chips 失效
标题翻译：使用多个部分缺陷的集成电路芯片实现的集成电路器件
公开(公告)号：US5581562A
公开(公告)日：1996-12-03
申请号：US325946
申请日：1994-10-19
申请人： Chong M. Lin , Wai-Yan Ho , Le T. Nguyen
发明人： Chong M. Lin , Wai-Yan Ho , Le T. Nguyen
IPC分类号： G01R31/28 , G06F11/26 , G06F17/50 , G06F11/00
CPC分类号： G06F17/5027
摘要： An integrated circuit (IC) device implemented according to an architectural design that specifies that the IC device is required to have one functional module, to perform a first function, connected to another functional module, to perform a second function. The IC device includes a first IC chip having a plurality of first functional modules implemented thereon. Some of the first functional modules are defective and others of the first functional modules are non-defective. At least one of the non-defective first functional modules is operable to perform the first function. The IC device also includes a second IC chip having a plurality of second functional modules implemented thereon. Some of the second functional modules are defective and others of the second functional modules are non-defective. At least one of the non-defective second functional modules is operable to perform the second function. The IC device further includes a bus, a first tri-state gate to electrically connect the non-defective first functional module to the bus, and the second tri-state gate to electrically connect the non-defective second functional modules to the bus.
摘要翻译：根据建筑设计实现的集成电路（IC）装置，其指定IC器件需要具有一个功能模块，以执行连接到另一功能模块的第一功能，以执行第二功能。 IC器件包括具有多个第一功能模块的第一IC芯片。第一功能模块中的一些是有缺陷的，第一功能模块中的其它模块是无缺陷的。至少一个无缺陷的第一功能模块可操作以执行第一功能。 IC器件还包括具有在其上实现的多个第二功能模块的第二IC芯片。第二功能模块中的一些是有缺陷的，第二功能模块中的其它功能模块是无缺陷的。至少一个无缺陷的第二功能模块可操作以执行第二功能。 IC器件还包括总线，将无缺陷第一功能模块电连接到总线的第一三态门和第二三态门，以将无缺陷的第二功能模块电连接到总线。

10. 发明授权

US5943250A Parallel multiplier that supports multiple numbers with different bit lengths 失效
标题翻译：支持多个不同位长数字的并行乘法器
公开(公告)号：US5943250A
公开(公告)日：1999-08-24
申请号：US734277
申请日：1996-10-21
申请人： Chang Soo Kim , Le T. Nguyen , Roney S. Wong
发明人： Chang Soo Kim , Le T. Nguyen , Roney S. Wong
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F2207/3828
摘要： A parallel multiplier for multiplying a multiplicand and multiplier with large bit lengths as well as simultaneously multiplying several multiplicands and multipliers with smaller bit lengths is disclosed. The parallel multiplier receives an N-bit multiplicand operand, an M-bit multiplier operand, and a data length signal. The parallel multiplier calculates an N+M bit product of an N-bit multiplicand from the multiplicand operand and an M-bit multiplier from the multiplier operand when the data length signal selects a first bit length. Furthermore, the parallel multiplier simultaneously calculates an (N+M)/2 bit first product of an N/2 bit first multiplicand from the multiplicand operand and an M/2 bit first multiplier from the multiplier operand, and an (N+M)/2 bit second product of an N/2 bit second multiplicand from the multiplicand operand and an M/2 bit second multiplier from the multiplier operand when the data length signal selects a second bit length.
摘要翻译：公开了一种并行乘法器，用于将乘法器和乘法器与大位长度相乘，以及同时乘以具有较小位长度的多个乘法器和乘法器。并行乘法器接收N位被乘数操作数，M位乘法器操作数和数据长度信号。当数据长度信号选择第一位长度时，并行乘法器计算来自乘法器操作数的N位被乘数的N + M位乘积和来自乘法器操作数的M位乘法器。此外，并行乘法器同时计算来自乘法器操作数的N / 2位第一被乘数的第（N + M）/ 2位第一乘积和来自乘法器操作数的M / 2位第一乘法器，并且（N + M）当从数据长度信号选择第二位长度时，来自乘法器操作数的N / 2位第二被乘数的2位第二乘积和来自乘法器操作数的M / 2位第二乘法器。

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