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1. 发明授权

US06061711A Efficient context saving and restoring in a multi-tasking computing system environment 失效
标题翻译：在多任务计算系统环境中高效的上下文保存和恢复
公开(公告)号：US06061711A
公开(公告)日：2000-05-09
申请号：US699280
申请日：1996-08-19
申请人： Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Le T. Nguyen , Jerry R. Van Aken , Alessandro Forin , Andrew R. Raffman
发明人： Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Le T. Nguyen , Jerry R. Van Aken , Alessandro Forin , Andrew R. Raffman
IPC分类号： G06F9/44 , G06F9/30 , G06F9/38 , G06F9/46 , G06F9/48 , G06F17/16
CPC分类号： G06F9/30087 , G06F9/30003 , G06F9/30036 , G06F9/30043 , G06F9/3009 , G06F9/3836 , G06F9/3861 , G06F9/3877 , G06F9/3887 , G06F9/461
摘要： In a multi-tasking computing system environment, one program is halted and context switched out so that a processor may context switch in a subsequent program for execution. Processor state information exists which reflects the state of the program being context switched out. Storage of this processor state information permits successful resumption of the context switched out program. When the context switched out program is subsequently context switched in, the stored processor information is loaded in preparation for successfully resuming the program at the point in which execution was previously halted. Although, large areas of memory can be allocated to processor state information storage, only a portion of this may need to be preserved across a context switch for successfully saving and resuming the context switched out program. Unnecessarily saving and loading all available processor state information can be noticeably inefficient particularly where relatively large amounts of processor state information exists. In one embodiment, a processor requests a co-processor to context switch out the currently executing program. At a predetermined appropriate point in the executing program, the co-processor responds by halting program execution and saving only the minimal amount of processor state information necessary for successful restoration of the program. The appropriate point is chosen by the application programmer at a location in the executing program that requires preserving a minimal portion of the processor information across a context switch. By saving only a minimal amount of processor information, processor time savings are accumulated across context save and restoration operations.
摘要翻译：在多任务计算系统环境中，停止一个程序并上下文切换，使得处理器可以在后续程序中上下文切换以执行。存在反映正在上下文切换的程序的状态的处理器状态信息。该处理器状态信息的存储允许成功恢复上下文切换程序。当上下文切换程序随后进行上下文切换时，加载所存储的处理器信息以准备好在先前停止执行的点成功恢复程序。尽管可以将大面积的存储器分配给处理器状态信息存储，但是只有一部分可能需要在上下文切换中被保留以成功地保存和恢复上下文切换程序。不必要地保存和加载所有可用的处理器状态信息，特别是在存在相对大量的处理器状态信息的情况下是显着的。在一个实施例中，处理器请求协处理器上下文切换当前执行的程序。在执行程序中的预定的适当点处，协处理器通过停止程序执行并且仅节省成功恢复程序所需的最小量的处理器状态信息来进行响应。应用程序员在执行程序中需要在上下文切换中保留处理器信息的最小部分的位置来选择适当的点。通过仅节省最少量的处理器信息，可以在上下文保存和恢复操作中累积处理器时间节省。

2. 发明授权

US5838984A Single-instruction-multiple-data processing using multiple banks of vector registers 失效
标题翻译：使用多个向量寄存器组的单指令多数据处理
公开(公告)号：US5838984A
公开(公告)日：1998-11-17
申请号：US697086
申请日：1996-08-19
申请人： Le Trong Nguyen , Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Roney Sau Don Wong
发明人： Le Trong Nguyen , Seungyoon Peter Song , Moataz A. Mohamed , Heonchul Park , Roney Sau Don Wong
IPC分类号： G06F17/16 , G06F9/30 , G06F9/318 , G06F12/00 , G06F15/16 , G06F15/78
CPC分类号： G06F9/30025 , G06F15/8076 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189
摘要： A vector processor includes two banks of vector registers where each vector register can stored multiple data elements and a control register with a field indicating a default bank. An instruction set for the vector processor includes instructions which use a register number to identify a vector registers in the default bank, uses a register number to identify a double-size vector register including a register from the first bank and a register from the second bank, and instructions which include a bank bit and a register number to access a vector register from either bank.
摘要翻译：向量处理器包括两组向量寄存器，其中每个向量寄存器可以存储多个数据元素，一个控制寄存器具有指示默认库的字段。用于向量处理器的指令集包括使用寄存器编号来识别默认组中的向量寄存器的指令，使用寄存器编号来识别包括来自第一组的寄存器的双倍大小向量寄存器和来自第二组的寄存器，以及包括存储位和寄存器号以用于从任一个存储体访问向量寄存器的指令。

3. 发明授权

US5922066A Multifunction data aligner in wide data width processor 失效
标题翻译：多功能数据对齐器在宽数据宽度处理器
公开(公告)号：US5922066A
公开(公告)日：1999-07-13
申请号：US805392
申请日：1997-02-24
申请人： Seongrai Cho , Heonchul Park , Seungyoon Peter Song
发明人： Seongrai Cho , Heonchul Park , Seungyoon Peter Song
IPC分类号： G06F9/38 , G06F5/01 , G06F11/26
CPC分类号： G06F5/015 , G06F9/30032 , G06F9/30036 , G06F9/345
摘要： A wide data width processor has an execution unit including an aligner that aligns data for load/store instructions and shifts or rotates data for arithmetic logic instructions. Use of the same circuitry and execution unit for these different types of instructions reduces overall circuit size because alignment circuitry need not be repeated, once in a load/store unit and once in an arithmetic logic unit.
摘要翻译：宽数据宽度处理器具有执行单元，该执行单元包括对准器，其对准用于加载/存储指令的数据，并移位或旋转用于算术逻辑指令的数据。对于这些不同类型的指令使用相同的电路和执行单元减少了总体电路尺寸，因为对准电路不需要重复，一次在加载/存储单元中，并且一次在算术逻辑单元中。

4. 发明授权

US5991531A Scalable width vector processor architecture for efficient emulation 失效
标题翻译：可扩展宽度向量处理器架构，实现高效仿真
公开(公告)号：US5991531A
公开(公告)日：1999-11-23
申请号：US804765
申请日：1997-02-24
申请人： Seungyoon Peter Song , Heonchul Park
发明人： Seungyoon Peter Song , Heonchul Park
IPC分类号： G06F9/06 , G06F9/302 , G06F9/318 , G06F9/455
CPC分类号： G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/3017
摘要： A N-byte vector processor is provided which can emulate 2N-byte processor operations by executing two N-byte operations sequentially. By using N-byte architecture to process 2N-byte wide data, chip size and costs are reduced. One embodiment allows 64-byte operations to be implemented with a 32-byte vector processor by executing a 32-byte instruction on the first 32-bytes of data and then executing a 32-byte instruction on the second 32-bytes of data. Registers and instructions for 64-byte operation are emulated using two 32-byte registers and instructions, respectively, with some instructions requiring modification to accommodate 64-byte operations between adjacent elements, operations requiring specific element locations, operations shifting elements in and out of registers, and operations specifying addresses exceeding 32 bytes.
摘要翻译：提供一个N字节向量处理器，可以通过依次执行两个N字节操作来模拟2N字节的处理器操作。通过使用N字节架构处理2N字节的宽数据，芯片尺寸和成本降低。一个实施例允许通过在前32个字节的数据上执行32字节指令，然后在第二个32字节数据上执行32字节指令，通过32字节向量处理器实现64字节操作。 64字节操作的寄存器和指令分别使用两个32字节寄存器和指令进行仿真，其中一些指令需要修改以适应相邻元件之间的64字节操作，需要特定元件位置的操作，将元件输入和输出寄存器，以及指定地址超过32个字节的操作。

5. 发明授权

US5881307A Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor 失效
标题翻译：在超标量处理器中使用简单的反依赖管道互锁控制读取延迟存储数据
公开(公告)号：US5881307A
公开(公告)日：1999-03-09
申请号：US805389
申请日：1997-02-24
申请人： Heonchul Park , Seungyoon Peter Song
发明人： Heonchul Park , Seungyoon Peter Song
IPC分类号： G06F9/38 , G06F9/40 , G06F9/30
CPC分类号： G06F9/3816 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3867 , G06F9/3885
摘要： A superscalar processor includes an execution unit that executes load/store instructions and an execution unit that executes arithmetic instruction. Execution pipelines for both execution units include a decode stage, a read stage that identify and read source operands for the instructions and an execution stage or stages performed in the execution units. For store instructions, reading store data from a register file is deferred until the store data is required for transfer to a memory system. This allows the store instructions to be decoded simultaneously with earlier instructions that generate the store data. A simple antidependency interlock uses a list of the register numbers identifying registers holding store data for pending store instructions. These register number are compared to the register numbers of destination operands of instructions, and instructions having destination operands matching a source of store data are stalled in the read stage to prevent the instruction from destroying store data before an earlier store instruction is complete.
摘要翻译：超标量处理器包括执行加载/存储指令的执行单元和执行算术指令的执行单元。两个执行单元的执行流水线包括解码阶段，用于识别和读取指令的源操作数的读取阶段以及在执行单元中执行的执行阶段或阶段。对于存储指令，从寄存器文件读取存储数据将被延迟，直到存储数据需要传输到存储器系统为止。这允许存储指令与生成存储数据的先前指令同时解码。一个简单的反依赖联锁使用寄存器编号列表来识别用于挂起存储指令的存储数据的寄存器。将这些寄存器编号与指令的目标操作数的寄存器编号进行比较，并且具有与存储数据源匹配的目标操作数的指令在读取阶段停止，以防止指令在较早的存储指令完成之前破坏存储数据。

6. 发明授权

US08225315B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US08225315B1
公开(公告)日：2012-07-17
申请号：US11933319
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Joseph Rowlands , Seungyoon Peter Song
IPC分类号： G06F9/455 , G06F15/76
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.
摘要翻译：一种包括物理核心和第一虚拟核心的虚拟核心管理系统，包括与执行第一程序相关联的逻辑状态的集合。第一个虚拟内核映射到物理内核。虚拟核心管理系统还包括第二虚拟核心，其包括与执行第二程序相关联的逻辑状态的集合，虚拟核心管理组件被配置为从物理核心取消映射第一虚拟核心并将第二虚拟核心映射到响应虚拟核心管理组件检测物理内核空闲的物理核心。

7. 发明授权

US07802073B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US07802073B1
公开(公告)日：2010-09-21
申请号：US11781726
申请日：2007-07-23
申请人： Yu Qing Cheng , John Gregory Favor , Carlos Puchol , Seungyoon Peter Song , Peter Glaskowsky , Laurent Moll , Joe Rowlands , Donald Alpert
发明人： Yu Qing Cheng , John Gregory Favor , Carlos Puchol , Seungyoon Peter Song , Peter Glaskowsky , Laurent Moll , Joe Rowlands , Donald Alpert
IPC分类号： G06F9/50
CPC分类号： G06F9/3851
摘要： The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.
摘要翻译：本公开提供适于与具有一个或多个物理核心的处理器一起使用的方法和系统。所述方法和系统包括适于将一个或多个虚拟核心映射到所述物理核心中的至少一个的虚拟核心管理组件，以使所述至少一个物理核心能够执行一个或多个程序。一个或多个虚拟核心包括与一个或多个程序的执行相关联的一个或多个逻辑状态。方法和系统可以包括适于存储一个或多个虚拟核的存储器组件。虚拟核心管理组件可以适于将一个或多个虚拟核心从存储器组件传送到至少一个物理核心。

8. 发明授权

US07797512B1 Virtual core management 有权
标题翻译：虚拟核心管理
公开(公告)号：US07797512B1
公开(公告)日：2010-09-14
申请号：US11933297
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Laurent R. Moll , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F9/46
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.
摘要翻译：包括一个或多个物理核心和一个或多个虚拟核心的虚拟核心管理系统。每个虚拟核心分别包括与相应程序的执行相关联的逻辑状态的集合。虚拟核心管理系统还包括一个或多个中断控制器，其被配置为发送一个或多个中断信号以中断与一个或多个虚拟核心中的至少一个虚拟核心相关联的对应程序的执行;以及虚拟核心管理组件，至少一个虚拟内核到一个或多个物理核心中的一个，并将一个或多个中断信号路由到相应的物理核心。

9. 发明授权

US07673122B1 Software hint to specify the preferred branch prediction to use for a branch instruction 有权
标题翻译：软件提示指定用于分支指令的首选分支预测
公开(公告)号：US07673122B1
公开(公告)日：2010-03-02
申请号：US11306000
申请日：2005-12-16
申请人： Seungyoon Peter Song , John Gregory Favor , Richard W. Thaik
发明人： Seungyoon Peter Song , John Gregory Favor , Richard W. Thaik
IPC分类号： G06F9/00
CPC分类号： G06F9/3846 , G06F9/3848
摘要： Software hints embedded in branch instructions direct selection of one of a plurality of branch predictors to use when processing the branch instructions, leading to improved branch prediction (i.e. fewer mis-predictions) over conventional schemes. A software agent assembles branch instructions having associated respective branch predictor control fields compatible with a branch predictor selector and a plurality of branch predictors. Each branch predictor control field is used to perform branch predictor selection, branch predictor control, or both. Branch predictor selection enables selective branch prediction according to an appropriate one of the branch predictors as determined by the software agent by examining context surrounding the branch instruction. Branch predictor control enables control of operation of one or more of the branch predictors. For example, a history-based branch predictor may be instructed to provide branch prediction according to a history-depth specified by the branch predictor control.
摘要翻译：嵌入分支指令中的软件提示直接选择在处理分支指令时使用的多个分支预测器中的一个，导致与常规方案相比改进的分支预测（即较少的误预测）。软件代理装配具有与分支预测器选择器和多个分支预测器兼容的相关联的相应分支预测器控制字段的分支指令。每个分支预测器控制字段用于执行分支预测器选择，分支预测器控制或两者。分支预测器选择通过检查分支指令周围的上下文，根据由软件代理确定的适当的一个分支预测器启用选择性分支预测。分支预测器控制使得能够控制一个或多个分支预测器的操作。例如，可以指示基于历史的分支预测器，以根据由分支预测器控制指定的历史深度来提供分支预测。

10. 发明授权

US07587585B1 Flag management in processors enabled for speculative execution of micro-operation traces 有权
标题翻译：处理器中的标志管理能够推测微操作轨迹的执行
公开(公告)号：US07587585B1
公开(公告)日：2009-09-08
申请号：US11553453
申请日：2006-10-26
申请人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
发明人： John Gregory Favor , Seungyoon Peter Song , Christopher P. Nelson
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30094 , G06F9/3808 , G06F9/3863
摘要： Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags during atomic trace renaming in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is stored when an atomic trace is renamed. An action that updates flags updates all entries in the table corresponding to younger atomic traces. If the atomic trace is aborted, then the corresponding flag checkpoint is used for restoration of flag state.
摘要翻译：通过与原子轨迹对应的一个或多个动作的组来管理推测性执行，可以有效地处理与标志相关的动作，因为原子轨迹有利地使原子轨迹边界上的标志值的检查点成为可能。在处理器系统中的原子轨迹重命名期间的检查点标志使用标志检查点表来存储多个标志检查点，每个对应于原子轨迹。当原子轨迹中止时，有选择地访问该表以提供标志信息来恢复推测标志。当重新命名原子轨迹时，存储对应的标志检查点。更新标志的操作会更新表中对应于较年轻原子轨迹的所有条目。如果原子轨迹中止，则对应的标志检查点用于恢复标志状态。

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