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1. 发明授权

US07986022B2 Semispherical integrated circuit structures 有权
标题翻译：半球形集成电路结构
公开(公告)号：US07986022B2
公开(公告)日：2011-07-26
申请号：US12621956
申请日：2009-11-19
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
IPC分类号： H01L31/105
CPC分类号： H01L31/03529 , H01L27/14643 , H01L29/0657 , H01L29/6609 , H01L29/66136 , H01L29/66234 , H01L29/732 , H01L29/8611 , H01L29/868 , H01L31/0352 , H01L31/103 , Y02E10/50
摘要： A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.
摘要翻译：二极管包括由具有第一掺杂极性的第一材料形成的衬底。衬底具有平坦表面和从平面表面延伸的至少一个半球形结构。半球形结构由第一材料形成。第二材料层在半球形结构之上。第二材料包括与第一掺杂极性相反的第二掺杂极性。第二材料层符合半球形结构的形状。第一电触头连接到基板，第二电触点连接到第二材料层。通过在原始层上制造附加层来形成附加的半导体结构。

2. 发明申请

US20110115054A1 SEMISPHERICAL INTEGRATED CIRCUIT STRUCTURES 有权
标题翻译：半导体集成电路结构
公开(公告)号：US20110115054A1
公开(公告)日：2011-05-19
申请号：US12621956
申请日：2009-11-19
申请人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
发明人： Kangguo Cheng , Toshiharu Furukawa , Robert R. Robison , William R. Tonti , Richard Q. Williams
IPC分类号： H01L29/73 , H01L29/06 , H01L21/331
CPC分类号： H01L31/03529 , H01L27/14643 , H01L29/0657 , H01L29/6609 , H01L29/66136 , H01L29/66234 , H01L29/732 , H01L29/8611 , H01L29/868 , H01L31/0352 , H01L31/103 , Y02E10/50
摘要： A diode comprises a substrate formed of a first material having a first doping polarity. The substrate has a planar surface and at least one semispherical structure extending from the planar surface. The semispherical structure is formed of the first material. A layer of second material is over the semispherical structure. The second material comprises a second doping polarity opposite the first doping polarity. The layer of second material conforms to the shape of the semispherical structure. A first electrical contact is connected to the substrate, and a second electrical contact is connected to the layer of second material. Additional semiconductor structures are formed by fabricating additional layers over the original layers.
摘要翻译：二极管包括由具有第一掺杂极性的第一材料形成的衬底。衬底具有平坦表面和从平面表面延伸的至少一个半球形结构。半球形结构由第一材料形成。第二材料层在半球形结构之上。第二材料包括与第一掺杂极性相反的第二掺杂极性。第二材料层符合半球形结构的形状。第一电触头连接到基板，第二电触点连接到第二材料层。通过在原始层上制造附加层来形成附加的半导体结构。

3. 发明申请

US20110095393A1 CREATING EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) HAVING SUBSTANTIALLY UNIFORM THICKNESS 有权
标题翻译：创造出具有重大均匀厚度的极细半导体绝缘体（ETSOI）
公开(公告)号：US20110095393A1
公开(公告)日：2011-04-28
申请号：US12603668
申请日：2009-10-22
申请人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L29/06 , H01L21/66 , C23F1/08
CPC分类号： H01L21/7624 , H01L21/30625 , H01L22/12 , H01L22/20 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
摘要翻译：通过测量晶片上的多个选定点处的半导体层厚度，制造出具有基本上均匀的厚度的极薄的绝缘体上半导体（ETSOI）晶片; 确定在所述多个选择点中的每一个处要除去的去除厚度，使得所述去除厚度的去除导致基本上均匀的晶片内半导体层厚度; 基于各个点的去除厚度，以剂量水平和能量水平中的至少一个将多个选择点中的每一个植入种子到晶片; 并抛光半导体层以使半导体层变薄。

4. 发明授权

US09018024B2 Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness 有权
标题翻译：制造具有基本上均匀厚度的非常薄的绝缘体上绝缘体（ETSOI）
公开(公告)号：US09018024B2
公开(公告)日：2015-04-28
申请号：US12603668
申请日：2009-10-22
申请人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Nathaniel C. Berliner , Kangguo Cheng , Jason E. Cummings , Toshiharu Furukawa , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/66 , H01L21/762 , H01L21/306
CPC分类号： H01L21/7624 , H01L21/30625 , H01L22/12 , H01L22/20 , H01L2924/0002 , Y10S438/959 , H01L2924/00
摘要： An extremely thin semiconductor-on-insulator (ETSOI) wafer is created having a substantially uniform thickness by measuring a semiconductor layer thickness at a plurality of selected points on a wafer; determining a removal thickness to be removed at each of the plurality of selected points such that removal of the removal thickness results in a substantially uniform within-wafer semiconductor layer thickness; implanting a species into the wafer at each of the plurality of selected points with at least one of a dose level and an energy level based on the removal thickness for the respective point; and polishing the semiconductor layer to thin the semiconductor layer.
摘要翻译：通过测量晶片上的多个选定点处的半导体层厚度，制造出具有基本上均匀的厚度的极薄的绝缘体上半导体（ETSOI）晶片; 确定在所述多个选择点中的每一个处要除去的去除厚度，使得所述去除厚度的去除导致基本上均匀的晶片内半导体层厚度; 基于各个点的去除厚度，以剂量水平和能量水平中的至少一个将多个选择点中的每一个植入种子到晶片; 并抛光半导体层以使半导体层变薄。

5. 发明授权

US07732865B2 Epitaxial imprinting 失效
标题翻译：外延印记
公开(公告)号：US07732865B2
公开(公告)日：2010-06-08
申请号：US11684306
申请日：2007-03-09
申请人： Toshiharu Furukawa , Carl Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L29/72
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/84 , H01L27/1203
摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.
摘要翻译：本发明提供一种用于制造包括底部半导体层的混合衬底的外延压印工艺; 存在于所述底部半导体层顶部的连续掩埋绝缘层; 以及存在于所述连续掩埋绝缘层上的顶部半导体层，其中所述顶部半导体层包括具有不同晶体取向的分离的平面半导体区域，所述分开的平面半导体区域彼此隔离。利用外延生长，晶片接合和再结晶退火的本发明的外延印刷方法。

6. 发明授权

US07217629B2 Epitaxial imprinting 失效
公开(公告)号：US07217629B2
公开(公告)日：2007-05-15
申请号：US11182381
申请日：2005-07-15
申请人： Toshiharu Furukawa , Carl Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/762
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/84 , H01L27/1203
摘要： The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

7. 发明授权

US06396120B1 Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application 失效
标题翻译：硅抗熔丝结构，绝缘体上的体和硅绝缘体制造方法和应用
公开(公告)号：US06396120B1
公开(公告)日：2002-05-28
申请号：US09527191
申请日：2000-03-17
申请人： Claude L Bertin , Toshiharu Furukawa , Erik L. Hedberg , Jack A. Mandelman , William R. Tonti , Richard Q. Williams
发明人： Claude L Bertin , Toshiharu Furukawa , Erik L. Hedberg , Jack A. Mandelman , William R. Tonti , Richard Q. Williams
IPC分类号： H01L2972
CPC分类号： H01L29/78696 , H01L21/823412 , H01L21/823456 , H01L23/5252 , H01L27/10897 , H01L27/1203 , H01L29/42384 , H01L2924/0002 , H01L2924/00
摘要： A method and semiconductor structure that uses a field enhanced region where the oxide thickness is substantially reduced, thereby allowing antifuse programming at burn-in voltages which do not damage the standard CMOS logic. The semiconductor device comprises a substrate that has a raised protrusion terminating at a substantially sharp point, an insulator layer over the raised protrusion sufficiently thin to be breached by a breakdown voltage applied to the sharp point, a region comprised of a material on the insulator over the raised protrusion for becoming electrically coupled to the substrate after the insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to the substrate. In a second embodiment, the semiconductor device comprises a substrate having a trough formed in a top surface of the substrate, a relatively thick insulator layer over the top surface of the substrate, a relatively thin insulator layer over the trough that is breached by a breakdown voltage applied to the trough, a region comprised of a material on the relatively thin insulator layer over the trough for becoming electrically coupled to the substrate after the relatively thin insulator layer is breached by the breakdown voltage, and a contact for supplying the breakdown voltage to said substrate.
摘要翻译：一种使用场强增强区域的方法和半导体结构，其中氧化物厚度大大降低，从而允许在不损坏标准CMOS逻辑的老化电压下进行反熔丝编程。半导体器件包括具有突出的突起终止于基本尖锐点的衬底，凸起突起上的绝缘体层足够薄以致被施加到尖锐点的击穿电压所破坏，由绝缘体上的材料构成的区域在绝缘体层被击穿电压破坏之后用于电耦合到衬底的凸起突起，以及用于向衬底提供击穿电压的触点。在第二实施例中，半导体器件包括在衬底的顶表面中形成有槽的衬底，在衬底的顶表面上方的相对较厚的绝缘体层，在槽的相对较薄的绝缘体层，其被破坏电压施加到槽，由比较薄的绝缘体层上的材料组成的区域，该沟槽在相对较薄的绝缘体层被击穿电压破坏之后用于变成与电极耦合的衬底;以及用于将击穿电压提供给所述基板。

8. 发明授权

US07217604B2 Structure and method for thin box SOI device 有权
标题翻译：薄盒SOI器件的结构和方法
公开(公告)号：US07217604B2
公开(公告)日：2007-05-15
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

9. 发明授权

US08110483B2 Forming an extremely thin semiconductor-on-insulator (ETSOI) layer 有权
标题翻译：形成极薄的绝缘体上半导体（ETSOI）层
公开(公告)号：US08110483B2
公开(公告)日：2012-02-07
申请号：US12603737
申请日：2009-10-22
申请人： Wagdi W. Abadeer , Lilian Kamal, legal representative , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier , Jed H. Rankin, Jr. , Robert R. Robison , William R. Tonti
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：公开了用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

10. 发明申请

US20120098087A1 FORMING AN EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR (ETSOI) LAYER 审中-公开
标题翻译：形成极薄的半导体绝缘体（ETSOI）层
公开(公告)号：US20120098087A1
公开(公告)日：2012-04-26
申请号：US13342423
申请日：2012-01-03
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Jason E. Cummings , Toshiharu Furukawa , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William R. Tonti
IPC分类号： H01L27/12 , H01L21/306 , H01L21/3065 , H01L21/265
CPC分类号： H01L29/0649 , H01L21/76264 , H01L21/84 , H01L27/1203
摘要： Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.
摘要翻译：用于形成非常薄的绝缘体上半导体（ETSOI）层的解决方案。在一个实施例中，一种方法包括提供包括通过至少一个浅沟槽隔离（STI）分离的多个绝缘体上半导体（SOI）层区域的晶片; 通过用植入物种植入多个SOI层区域来使多个SOI层区域非晶化; 以及去除所述非晶化SOI层区域的一部分以在所述非晶化SOI层区域中形成至少一个凹部。

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