专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09041105B2 Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure 有权
标题翻译：集成电路包括绝缘体上绝缘体上的晶体管结构，相关方法和设计结构
公开(公告)号：US09041105B2
公开(公告)日：2015-05-26
申请号：US13553947
申请日：2012-07-20
申请人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
发明人： William F. Clark, Jr. , Qizhi Liu , Robert M. Rassel , Yun Shi
IPC分类号： H01L27/088 , H01L27/12 , H01L21/84 , H01L21/265
CPC分类号： H01L27/1203 , H01L21/84
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，IC包括：衬底; 设置在所述基板上的第一半导体层; 在所述衬底的一部分内延伸穿过所述第一半导体层的浅沟槽隔离（STI），所述STI基本上分离第一n +区和第二n +区; 以及设置在所述第一半导体层的与所述STI连接的部分上的栅极，所述栅极包括：设置在所述第一半导体层上并连接到所述STI的掩埋金属氧化物（BOX）层; 设置在BOX层上的盖层; 以及设置在第一半导体层和衬底内的p型阱组件，p型阱组件连接到第二n +区。

2. 发明授权

US08916426B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US08916426B2
公开(公告)日：2014-12-23
申请号：US13431414
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Terence B. Hook , Junjun Li , Theodorus E. Standaert , Thomas A. Wallner
IPC分类号： H01L21/338 , H01L29/66 , H01L21/8238 , H01L21/84
CPC分类号： H01L27/1211 , H01L21/7624 , H01L21/823821 , H01L21/845 , H01L27/0207 , H01L27/0262 , H01L27/0924 , H01L27/1203 , H01L29/66795 , H01L29/785
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。器件区域由轻掺杂的半导体材料组成。器件结构还包括形成在器件区域中并限定结的掺杂区域。器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

3. 发明授权

US08580601B2 Pixel sensor cell with a dual work function gate electrode 有权
标题翻译：具有双功能栅极电极的像素传感器单元
公开(公告)号：US08580601B2
公开(公告)日：2013-11-12
申请号：US13571986
申请日：2012-08-10
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John Joseph Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L27/14614
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.
摘要翻译：像素传感器单元，制造像素传感器单元的方法以及像素传感器单元的设计结构。像素传感器单元具有在栅极电介质上包括栅极电介质和栅电极的栅极结构。栅极电极包括具有在栅极电介质上具有并置关系的第一和第二部分的层。栅电极的第二部分由诸如掺杂多晶硅或金属的导体组成。栅电极的第一部分由具有比包括第二部分的导体更高的功函的金属组成，使得栅极结构具有非对称阈值电压。

4. 发明申请

US20130258532A1 PASSIVE DEVICES FOR FINFET INTEGRATED CIRCUIT TECHNOLOGIES 有权
公开(公告)号：US20130258532A1
公开(公告)日：2013-10-03
申请号：US13431347
申请日：2012-03-27
申请人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
发明人： William F. Clark, JR. , Robert J. Gauthier, JR. , Junjun Li
IPC分类号： H01L27/06 , H01L21/20 , H01L21/33 , G06F17/50 , H01L21/8249 , H01L29/06 , H01L29/73 , H02H7/20 , H01L21/331
CPC分类号： H01L27/0262 , G06F17/5072 , H01L21/8249 , H01L21/845 , H01L27/0255 , H01L27/06 , H01L27/1211 , H01L29/06
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.

5. 发明申请

US20120301990A1 PIXEL SENSOR CELL WITH A DUAL WORK FUNCTION GATE ELECTODE 有权
公开(公告)号：US20120301990A1
公开(公告)日：2012-11-29
申请号：US13571986
申请日：2012-08-10
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L31/18
CPC分类号： H01L27/14614
摘要： Pixel sensor cells, methods of fabricating pixel sensor cells, and design structures for a pixel sensor cell. The pixel sensor cell has a gate structure that includes a gate dielectric and a gate electrode on the gate dielectric. The gate electrode includes a layer with first and second sections that have a juxtaposed relationship on the gate dielectric. The second section of the gate electrode is comprised of a conductor, such as doped polysilicon or a metal. The first section of the gate electrode is comprised of a metal having a higher work function than the conductor comprising the second section so that the gate structure has an asymmetric threshold voltage.

6. 发明申请

US20120235216A1 DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
标题翻译：大金属门和屏蔽结构，制造和设计结构的方法
公开(公告)号：US20120235216A1
公开(公告)日：2012-09-20
申请号：US13051510
申请日：2011-03-18
申请人： Brent A. ANDERSON , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. ANDERSON , Andres Bryant , William F. Clark, JR. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L31/0216 , G06F17/50 , H01L31/18
CPC分类号： H01L31/0232 , G06F17/5045 , G06F17/5054 , H01L27/14632 , H01L27/14683 , H01L29/66545
摘要： Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses.
摘要翻译：提供了具有镶嵌金属栅极和像素传感器单元屏蔽的半导体结构，制造方法和设计结构。该方法包括在虚拟栅极结构上形成介电层。该方法还包括在电介质层中形成一个或多个凹槽。该方法还包括去除电介质层中的虚拟栅极结构以形成沟槽。该方法还包括在沟槽中形成金属和在电介质层中形成多个凹槽以在沟槽中形成镶嵌金属栅极结构以及在一个或多个凹槽中形成一个或多个金属部件。

7. 发明申请

US20120168832A1 ASYMMETRIC FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD 有权
标题翻译：不对称场效应晶体管结构与方法
公开(公告)号：US20120168832A1
公开(公告)日：2012-07-05
申请号：US13246175
申请日：2011-09-27
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, JR. , Edward J. Nowak
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7834 , H01L29/7835
摘要： Disclosed are embodiments of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate are tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
摘要翻译：公开了非对称场效应晶体管结构的实施例和形成其中源极区（Rs）和栅极 - 漏极电容（Cgd）中的串联电阻都被降低以便提供最佳性能（即提供改进的驱动电流，电路延迟最小）。具体地说，源极和漏极区域的不同高度和/或源极和漏极区域与栅极之间的不同距离被调整以最小化源极区域中的串联电阻（即，为了确保串联电阻小于预定电阻值），并且为了同时使栅极 - 漏极电容最小化（即，为了同时确保栅极到漏极电容小于预定的电容值）。

8. 发明授权

US08039376B2 Methods of changing threshold voltages of semiconductor transistors by ion implantation 有权
标题翻译：通过离子注入来改变半导体晶体管的阈值电压的方法
公开(公告)号：US08039376B2
公开(公告)日：2011-10-18
申请号：US11939578
申请日：2007-11-14
申请人： William F. Clark, Jr. , Edward Joseph Nowak
发明人： William F. Clark, Jr. , Edward Joseph Nowak
IPC分类号： H01L21/425
CPC分类号： H01L21/26586 , H01L21/823431 , H01L29/105 , H01L29/66795 , H01L29/66803
摘要： A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction.
摘要翻译：一种形成半导体结构的方法。该方法包括提供包括半导体衬底的半导体结构。半导体衬底包括（i）限定垂直于顶部衬底表面的参考方向的顶部衬底表面和（ii）半导体本体区域。该方法还包括通过调整注入工艺将第一掺杂极性的掺杂剂的调整剂量注入到半导体体区域中。离子轰击调整植入过程在参考方向。该方法还包括（i）对半导体衬底进行图形化，导致半导体体区域的侧壁暴露于周围环境，然后（ii）将碱性剂量的第二掺杂极性掺杂剂注入到半导体本体区域中，植入过程。基极注入工艺的离子轰击在与参考方向成非零角度的方向上。

9. 发明授权

US07939417B2 Bipolar transistor and back-gated transistor structure and method 有权
标题翻译：双极晶体管和后栅晶体管结构及方法
公开(公告)号：US07939417B2
公开(公告)日：2011-05-10
申请号：US12536636
申请日：2009-08-06
申请人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
发明人： Andres Bryant , William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L21/331
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203 , H01L29/0804 , H01L29/7327 , H01L29/78648
摘要： A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.
摘要翻译：公开了一种结构，其包括在体层上包括绝缘体层的衬底和在衬底的第一区域中的双极晶体管，所述双极晶体管包括绝缘体层中的发射极区域的至少一部分。另一公开的结构包括在衬底的第一区域中的反相双极晶体管，其包括体层上的绝缘体层，反相双极晶体管包括发射极区域，以及位于衬底的第二区域中的后栅极晶体管，其中背面背栅式晶体管的栅极导体和发射极区域的至少一部分处于相同的材料层中。还公开了一种将双极晶体管和后栅极晶体管组合在一起的结构的方法。

10. 发明授权

US07932134B2 Method of forming a semiconductor structure 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07932134B2
公开(公告)日：2011-04-26
申请号：US12610563
申请日：2009-11-02
申请人： William F. Clark, Jr. , Edward J. Nowak
发明人： William F. Clark, Jr. , Edward J. Nowak
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/861 , H01L29/402 , H01L29/417 , H01L29/6609 , H01L29/772 , H01L29/78648
摘要： Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.
摘要翻译：公开了在半导体器件（例如场效应晶体管（FET）或二极管）之下并入场屏蔽的半导体结构。场屏蔽被夹在晶片上的上隔离层和下隔离层之间。局部互连延伸穿过上隔离层并将场屏蔽连接到器件的选定掺杂半导体区域（例如，FET的二极管的源极/漏极区域或二极管的阴极或阳极）。进入设备的电流，例如，在线路充电的后端，被远离上隔离层的局部互连分流，并进入场屏蔽。因此，不允许在上部隔离层中积聚电荷，而是从场屏蔽件渗入下部隔离层并进入下面的基板。该场屏蔽进一步提供抵抗掉在下隔离层或衬底内的任何电荷的保护屏障。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式