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1. 发明授权

US07936017B2 Reduced floating body effect without impact on performance-enhancing stress 有权
标题翻译：降低浮体效应，而不影响性能增强应力
公开(公告)号：US07936017B2
公开(公告)日：2011-05-03
申请号：US12120836
申请日：2008-05-15
申请人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
发明人： William F. Clark, Jr. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/66772 , H01L29/7848 , H01L29/78612 , H01L29/78621
摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.
摘要翻译：提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

2. 发明申请

US20090283828A1 Reduced Floating Body Effect Without Impact on Performance-Enhancing Stress 有权
标题翻译：减少浮体效应，而不影响性能增强应力
公开(公告)号：US20090283828A1
公开(公告)日：2009-11-19
申请号：US12120836
申请日：2008-05-15
申请人： William F. Clark, JR. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
发明人： William F. Clark, JR. , Toshiharu Furukawa , Xuefeng Hua , Charles W. Koburger, III , Robert R. Robison
IPC分类号： H01L29/786 , H01L21/425 , G06F17/50
CPC分类号： H01L29/66636 , H01L21/26586 , H01L29/165 , H01L29/665 , H01L29/66772 , H01L29/7848 , H01L29/78612 , H01L29/78621
摘要： A method, gated device and design structure are presented for providing reduced floating body effect (FBE) while not impacting performance enhancing stress. One method includes forming damage in a portion of a substrate adjacent to a gate; removing a portion of the damaged portion to form a trench, leaving another portion of the damaged portion at least adjacent to a channel region; and substantially filling the trench with a material to form a source/drain region.
摘要翻译：提出了一种方法，选通装置和设计结构，用于提供减少的浮体效应（FBE），同时不影响性能增强应力。一种方法包括在与栅极相邻的衬底的一部分中形成损伤; 去除损坏部分的一部分以形成沟槽，将损坏部分的另一部分至少邻近沟道区域; 并且用材料基本上填充沟槽以形成源极/漏极区域。

3. 发明申请

US20110204384A1 METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR 有权
标题翻译：在SOI绝缘体（SOI）波形上形成具有嵌入式和表面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和平面场效应晶体管的设计结构
公开(公告)号：US20110204384A1
公开(公告)日：2011-08-25
申请号：US13101267
申请日：2011-05-05
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L27/12 , H01L29/12 , G06F17/50 , B82Y99/00
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

4. 发明授权

US08525186B2 Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (SOI) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权
标题翻译：在绝缘体上硅（SOI）晶片上形成具有嵌入和刻面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构
公开(公告)号：US08525186B2
公开(公告)日：2013-09-03
申请号：US13101267
申请日：2011-05-05
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

5. 发明申请

US20100295127A1 METHOD OF FORMING A PLANAR FIELD EFFECT TRANSISTOR WITH EMBEDDED AND FACETED SOURCE/DRAIN STRESSORS ON A SILICON-ON-INSULATOR (SOI) WAFER, A PLANAR FIELD EFFECT TRANSISTOR STRUCTURE AND A DESIGN STRUCTURE FOR THE PLANAR FIELD EFFECT TRANSISTOR 有权
标题翻译：在SOI绝缘体（SOI）波形上形成具有嵌入式和表面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和平面场效应晶体管的设计结构
公开(公告)号：US20100295127A1
公开(公告)日：2010-11-25
申请号：US12470001
申请日：2009-05-21
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L29/786 , H01L21/336 , G06F17/50
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

6. 发明申请

US20090267149A1 SOURCE/DRAIN JUNCTION FOR HIGH PERFORMANCE MOSFET FORMED BY SELECTIVE EPI PROCESS 有权
标题翻译：通过选择性EPI工艺形成的高性能MOSFET的源极/漏极连接
公开(公告)号：US20090267149A1
公开(公告)日：2009-10-29
申请号：US12109025
申请日：2008-04-24
申请人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
发明人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
IPC分类号： H01L29/786 , H01L21/336 , H01L21/84
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译：在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。

7. 发明授权

US07932136B2 Source/drain junction for high performance MOSFET formed by selective EPI process 有权
标题翻译：通过选择性EPI工艺形成的高性能MOSFET的源极/漏极结
公开(公告)号：US07932136B2
公开(公告)日：2011-04-26
申请号：US12109025
申请日：2008-04-24
申请人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
发明人： Xuefeng Hua , Johnathan E. Faltermeier , Toshiharu Furukawa , Oleg Gluschenkov
IPC分类号： H01L21/00
CPC分类号： H01L29/66636 , H01L29/1083 , H01L29/665 , H01L29/6653 , H01L29/66772 , H01L29/7848 , H01L29/78609 , H01L29/78621 , H01L29/78696
摘要： In a field effect transistor (FET), halo features may be formed by etching into the surface of a silicon layer followed by a step of growing a first epitaxial silicon (epi-Si) layer on the etched silicon layer. Source (S) and drain (D), as well as S/D extension features may similarly be formed by etching an epitaxial silicon layer, then filling with another epitaxial layer. Source and Drain, and extensions, and halo, which are normally formed by diffusion, may be formed as discrete elements by etching and filling (epi-Si). This may provide a shallow, highly activated, abrupt S/D extension, an optimally formed halo and deep S/D diffusion doping, and maximized improvement of channel mobility from the compressive or tensile stress from e-SiGe or e-SiC.
摘要翻译：在场效应晶体管（FET）中，可以通过蚀刻到硅层的表面中，随后在蚀刻的硅层上生长第一外延硅（epi-Si）层的步骤来形成晕圈特征。源极（S）和漏极（D）以及S / D延伸特征可以类似地通过蚀刻外延硅层形成，然后用另一个外延层填充。通常通过扩散形成的源极和漏极，延伸部分和光晕可以通过蚀刻和填充（epi-Si）形成为离散元件。这可以提供浅的，高活化的，突然的S / D延伸，最佳形成的光晕和深S / D扩散掺杂，并且最大限度地改善来自e-SiGe或e-SiC的压缩或拉伸应力的沟道迁移率。

8. 发明授权

US07951657B2 Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (S0I) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor 有权
标题翻译：在绝缘体上硅（S0I）晶片上形成具有嵌入式和多面源极/漏极应力的平面场效应晶体管的方法，平面场效应晶体管结构和用于平面场效应晶体管的设计结构
公开(公告)号：US07951657B2
公开(公告)日：2011-05-31
申请号：US12470001
申请日：2009-05-21
申请人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
发明人： Kangguo Cheng , Johnathan E. Faltermeier , Toshiharu Furukawa , Xuefeng Hua
IPC分类号： H01L21/84
CPC分类号： H01L29/66636 , H01L21/26506 , H01L29/1079 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Disclosed are embodiments of a method of forming, on an SOI wafer, a planar FET with embedded and faceted source/drain stressors. The method incorporates a directional ion implant process to create amorphous regions at the bottom surfaces of source/drain recesses in a single crystalline semiconductor layer of an SOI wafer. Then, an etch process selective to different crystalline planes over others and further selective to single crystalline semiconductor material over amorphous semiconductor material can be performed in order to selectively adjust the shape (i.e., the profile) of the recess sidewalls without increasing the depth of the recesses. Subsequently, an anneal process can be performed to re-crystallize the amorphous regions and an epitaxial deposition process can be used to fill the recesses with source/drain stressor material. Also disclosed are embodiments of a planar FET structure and a design structure for the planar FET.
摘要翻译：公开了一种在SOI晶片上形成具有嵌入和切向的源极/漏极应力源的平面FET的方法的实施例。该方法包括定向离子注入工艺，以在SOI晶片的单晶半导体层中的源极/漏极凹槽的底表面处产生非晶区域。然后，可以执行对不同结晶平面在其它晶体上的选择性的蚀刻工艺，并且对非晶半导体材料上的单晶半导体材料进一步选择性的蚀刻工艺，以便选择性地调节凹陷侧壁的形状（即，轮廓）而不增加凹槽随后，可以进行退火处理以使非晶区域再结晶，并且可以使用外延沉积工艺来用源极/漏极应力材料填充凹部。还公开了平面FET结构和平面FET的设计结构的实施例。

9. 发明授权

US08084329B2 Transistor devices and methods of making 失效
标题翻译：晶体管器件及其制造方法
公开(公告)号：US08084329B2
公开(公告)日：2011-12-27
申请号：US12693629
申请日：2010-01-26
申请人： John C. Arnold , Xuefeng Hua , Rangarajan Jagannathan , Stefan Schmitz
发明人： John C. Arnold , Xuefeng Hua , Rangarajan Jagannathan , Stefan Schmitz
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.
摘要翻译：在一个实施例中，制造晶体管器件的方法包括：提供半导体形貌，其包括设置在一对电介质间隔物之间的半导体衬底之上的栅极导体; 各向异性地蚀刻介电间隔物的相对侧上的半导体衬底的暴露区域，以在衬底中形成凹陷区域; 在所述凹陷区域中氧化所述衬底的暴露表面以在其上形成氧化物; 从凹陷区域的底部除去氧化物，同时将氧化物保持在凹陷区域的侧壁上; 并且各向同性蚀刻所述基板，使得所述凹陷区域切割所述一对电介质间隔物。

10. 发明授权

US07470329B2 Method and system for nanoscale plasma processing of objects 有权
标题翻译：物体的纳米级等离子体处理方法与系统
公开(公告)号：US07470329B2
公开(公告)日：2008-12-30
申请号：US10913323
申请日：2004-08-09
申请人： Gottlieb S. Oehrlein , Xuefeng Hua , Christian Stolz
发明人： Gottlieb S. Oehrlein , Xuefeng Hua , Christian Stolz
IPC分类号： C23C16/00 , C23F1/00 , H01L21/306
CPC分类号： H01J37/32623
摘要： A plasma processing system includes a source of plasma, a substrate and a shutter positioned in close proximity to the substrate. The substrate/shutter relative disposition is changed for precise control of substrate/plasma interaction. This way, the substrate interacts only with a fully established, stable plasma for short times required for nanoscale processing of materials. The shutter includes an opening of a predetermined width, and preferably is patterned to form an array of slits with dimensions that are smaller than the Debye screening length. This enables control of the substrate/plasma interaction time while avoiding the ion bombardment of the substrate in an undesirable fashion. The relative disposition between the shutter and the substrate can be made either by moving the shutter or by moving the substrate.
摘要翻译：等离子体处理系统包括等离子体源，基板和靠近基板定位的快门。为了精确控制衬底/等离子体相互作用，改变衬底/快门相对配置。这样，衬底仅与材料的纳米级处理所需的短时间内完全建立稳定的等离子体相互作用。快门包括预定宽度的开口，并且优选地被图案化以形成具有小于德拜筛选长度的尺寸的狭缝阵列。这使得能够以不希望的方式避免衬底的离子轰击，从而控制衬底/等离子体相互作用时间。快门和基板之间的相对位置可以通过移动快门或移动基板来进行。

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