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1. 发明授权

US06559666B2 Method and device for semiconductor testing using electrically conductive adhesives 失效
标题翻译：使用导电胶粘剂进行半导体测试的方法和装置
公开(公告)号：US06559666B2
公开(公告)日：2003-05-06
申请号：US09875246
申请日：2001-06-06
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.
摘要翻译：一种用于测试和燃烧半导体电路的方法和装置。该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。此外，ECA可以沉积在C4凸点或锡盖铅基上。该方法和装置的变化包括用ECA填充非导电插入件的通孔。可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

2. 发明授权

US06268739B1 Method and device for semiconductor testing using electrically conductive adhesives 失效
公开(公告)号：US06268739B1
公开(公告)日：2001-07-31
申请号：US09478678
申请日：2000-01-06
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

3. 发明授权

US06492071B1 Wafer scale encapsulation for integrated flip chip and surface mount technology assembly 失效
标题翻译：用于集成倒装芯片和表面贴装技术组装的晶圆级封装
公开(公告)号：US06492071B1
公开(公告)日：2002-12-10
申请号：US09670410
申请日：2000-09-26
申请人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
发明人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
IPC分类号： G03F900
CPC分类号： H01L21/56 , H01L24/81 , H01L2224/274 , H01L2224/81801 , H01L2224/83191 , H01L2924/14 , H05K3/1225 , H01L2924/00
摘要： A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.
摘要翻译：提供了一种用于施加与焊料助焊剂组合的粘合剂制剂的混合物的装置和方法，使得可以用这种组合快速包封倒装芯片而不干扰后续的晶片加工步骤。还提供了以这样的方式设计的晶片模板，即分离各个芯片模具的锯切线不受制剂的接触。还提供了使用这种晶片模板的挤出筛选。

4. 发明授权

US06288559B1 Semiconductor testing using electrically conductive adhesives 失效
标题翻译：使用导电胶的半导体测试
公开(公告)号：US06288559B1
公开(公告)日：2001-09-11
申请号：US09050820
申请日：1998-03-30
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.
摘要翻译：一种用于测试和燃烧半导体电路的方法和装置。该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。此外，ECA可以沉积在C4凸点或锡盖铅基上。该方法和装置的变化包括用ECA填充非导电插入件的通孔。可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

5. 发明授权

US06674647B2 Low or no-force bump flattening structure and method 失效
标题翻译：低或无力凸起平整结构和方法
公开(公告)号：US06674647B2
公开(公告)日：2004-01-06
申请号：US10040740
申请日：2002-01-07
申请人： Mark V. Pierson , Ajit K. Trivedi
发明人： Mark V. Pierson , Ajit K. Trivedi
IPC分类号： H05K710
CPC分类号： H05K3/3436 , B23K26/0006 , B23K26/361 , B23K2101/42 , B23K2103/16 , H01L23/49816 , H01L24/81 , H01L2224/13111 , H01L2224/16 , H01L2224/81026 , H01L2224/81136 , H01L2224/81193 , H01L2224/814 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H05K3/3457 , H05K2201/09745 , H05K2201/10992 , H05K2203/0278 , H05K2203/048 , Y02P70/613 , H01L2924/00
摘要： Self-aligning combination of a substrate with a chip is provided, using reverse patterns of raised recesses and raised shapes on the respective substrate and chip surfaces. High-force contact bump production is avoided. Reliable contact between a chip and substrate is achieved, with minimized skewing after chip placement.
摘要翻译：提供了基板与芯片的自对准组合，在相应的基板和芯片表面上使用凸起凹槽和凸起形状的反向图案。避免了大力接触凸块生产。实现芯片和基板之间的可靠接触，并且在芯片放置之后使偏移最小化。

6. 发明授权

US06756680B2 Flip chip C4 extension structure and process 有权
公开(公告)号：US06756680B2
公开(公告)日：2004-06-29
申请号：US09782471
申请日：2001-02-12
申请人： Miguel A. Jimarez , Cynthia S. Milkovich , Mark V. Pierson
发明人： Miguel A. Jimarez , Cynthia S. Milkovich , Mark V. Pierson
IPC分类号： H01L2348
CPC分类号： H01L24/12 , B23K1/0016 , B23K2101/42 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05671 , H01L2224/10126 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/81013 , H01L2224/81801 , H01L2224/81894 , H01L2924/00013 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/351 , H05K3/0032 , H05K3/3436 , H05K2201/0379 , H05K2201/10977 , H05K2201/10992 , H05K2203/0415 , H05K2203/043 , H05K2203/0465 , Y02P70/613 , H01L2924/00 , H01L2224/29099 , H01L2924/00014
摘要： An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

7. 发明授权

US06699736B2 Electrical coupling of a stiffener to a chip carrier 有权
标题翻译：加强筋与芯片载体的电耦合
公开(公告)号：US06699736B2
公开(公告)日：2004-03-02
申请号：US10305643
申请日：2002-11-26
申请人： Terry J. Dornbos , Raymond A. Phillips, Jr. , Mark V. Pierson , William J. Rudik , David L. Thomas
发明人： Terry J. Dornbos , Raymond A. Phillips, Jr. , Mark V. Pierson , William J. Rudik , David L. Thomas
IPC分类号： H01L2144
CPC分类号： H05K3/0061 , H01L21/4846 , H05K3/386 , H05K3/4038 , H05K2201/0305 , H05K2201/09554 , H05K2201/10977
摘要： A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate. The electrically conductive contact may include an electrically conductive adhesive or a metallic solder. Additional embodiments of the present invention form the adhesive layer by applying an electrically conductive adhesive on the substrate, wherein after the stiffener is placed on the adhesive layer, the electrically conductive adhesive mechanically and electrically couples the stiffener to the surface of the substrate.
摘要翻译：用于将金属加强件导电耦合到芯片载体的方法和结构。衬底在其表面上具有导电焊盘，并且在衬底表面上形成粘合剂层。金属加强件被放置在粘合剂层上，其中粘合剂层将加强件机械地连接到基底表面，并将加强件电耦合到垫。然后将粘合剂层固化，例如通过在升高的温度下加压。本发明的实施例通过在焊盘上形成导电触点并在基板上设置干燥的粘合剂来形成粘合剂层，使得导电触点位于干粘合剂中的孔内。导电触头将加强件电耦合到焊盘。固化步骤包括固化干燥粘合剂和导电接触，导致干燥粘合剂将加强剂粘合到基底上。导电接触可包括导电粘合剂或金属焊料。本发明的另外的实施方案通过在基底上施加导电粘合剂形成粘合剂层，其中在将加强件放置在粘合剂层上之后，导电粘合剂将加强件机械地和电耦合到基底的表面。

8. 发明授权

US06487461B1 TFT panel alignment and attachment method and apparatus 失效
标题翻译： TFT面板对准和附接方法和装置
公开(公告)号：US06487461B1
公开(公告)日：2002-11-26
申请号：US09590280
申请日：2000-06-09
申请人： Michael A. Gaynes , Allan O. Johnson , Ramesh R. Kodnani , Mark V. Pierson , Edward J. Tasillo
发明人： Michael A. Gaynes , Allan O. Johnson , Ramesh R. Kodnani , Mark V. Pierson , Edward J. Tasillo
IPC分类号： G05B1918
CPC分类号： G02F1/13336 , Y10S345/903
摘要： A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.
摘要翻译：一种用于对准多个用于构建平板显示器的薄膜晶体管瓦片的方法。盖板安装在盖板支架上。接合材料的第一层被施加到每个瓷砖的第一侧中的至少一个以及待固定瓷砖的盖板的表面。瓦片布置在盖板上，使得第一层粘合材料布置在瓦片和盖板之间。瓦片连接到对准装置。瓷砖相对于彼此和盖板对准。瓦片至少部分地固定到盖板上。

9. 发明授权

US06173887B1 Method of making electrically conductive contacts on substrates 失效
标题翻译：在基板上制作导电触点的方法
公开(公告)号：US06173887B1
公开(公告)日：2001-01-16
申请号：US09339924
申请日：1999-06-24
申请人： Donald I. Mead , Mark V. Pierson
发明人： Donald I. Mead , Mark V. Pierson
IPC分类号： B23K2622
CPC分类号： H05K3/3484 , B23K1/0053 , B23K1/0056 , B23K2101/40 , H05K3/3494 , H05K2203/043 , H05K2203/0557 , H05K2203/107
摘要： A method of making an electrically conductive contact on a substrate by applying a layer of solder paste to a circuitized feature on a substrate and selectively heating and melting the solder paste over the feature to form a solder bump. The excess solder paste is removed. A focused energy heat source such as a laser beam or focused Infrared heats the solder paste. In another embodiment, a reflective mask with apertures may be used to allow focused heating source to selectively melt areas of the solder paste layer applied to a circuitized feature. In yet another embodiment, a reflective mask with apertures filled with solder paste is applied onto a substrate and then heated to cause localized solder melting. The mask and excess solder paste are removed.
摘要翻译：一种通过将衬底层施加到衬底上的电路化特征并在该特征上选择性地加热和熔化焊膏以形成焊料凸块来在衬底上形成导电接触的方法。去除多余的焊膏。聚焦能量热源如激光束或聚焦红外线加热焊膏。在另一个实施例中，具有孔的反射掩模可以用于允许聚焦的加热源选择性地熔化施加到电路化特征上的焊膏层的区域。在另一个实施例中，将具有填充有焊膏的孔的反射掩模施加到基板上，然后加热以引起局部焊料熔化。去除掩模和多余的焊膏。

10. 发明授权

US5969945A Electronic package assembly 失效
标题翻译：电子封装组装
公开(公告)号：US5969945A
公开(公告)日：1999-10-19
申请号：US808829
申请日：1997-02-27
申请人： Lawrence R. Cutting , Michael A. Gaynes , Eric A. Johnson , Cynthia S. Milkovich , Jeffrey S. Perkins , Mark V. Pierson , Steven E. Poetzinger , Jerzy Zalesinski
发明人： Lawrence R. Cutting , Michael A. Gaynes , Eric A. Johnson , Cynthia S. Milkovich , Jeffrey S. Perkins , Mark V. Pierson , Steven E. Poetzinger , Jerzy Zalesinski
IPC分类号： H01L21/48 , H01L23/367 , H01L23/538 , H05K1/00 , H05K1/02 , H05K1/18 , H05K3/00 , H05K3/12 , H05K3/34 , H05K7/20
CPC分类号： H05K7/20454 , H01L21/4857 , H01L21/4867 , H01L23/3672 , H01L23/5387 , H05K1/021 , H05K1/189 , H05K3/0061 , H05K3/1216 , H05K3/4691 , H01L2224/16 , H01L2924/01078 , H01L2924/01322 , H05K1/0298 , H05K1/182 , H05K2201/0154 , H05K2201/09063 , H05K2201/096 , H05K2201/09745 , H05K2201/1056 , H05K2201/2009 , H05K2203/1394 , H05K3/3415 , H05K3/3452 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144
摘要： A screen printing fixture holds a flexible circuit board having components attached to one side, to allow screening a pattern of solder paste onto the second side for subsequent attachment of components to that side. In an electronic package assembly a flexible circuit board with components is wound about a heat spreader assembly having a cavity so that at least one component on the flexible circuit board is positioned within the cavity and in thermal connection to the heat spreader.
摘要翻译：丝网印刷夹具具有安装在一侧的部件的柔性电路板，以允许将焊膏的图案屏蔽到第二侧上，以便随后将部件附接到该侧。在电子封装组件中，具有部件的柔性电路板围绕具有空腔的散热器组件缠绕，使得柔性电路板上的至少一个部件位于腔内并与散热器热连接。

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