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1. 发明授权

US06559666B2 Method and device for semiconductor testing using electrically conductive adhesives 失效
标题翻译：使用导电胶粘剂进行半导体测试的方法和装置
公开(公告)号：US06559666B2
公开(公告)日：2003-05-06
申请号：US09875246
申请日：2001-06-06
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.
摘要翻译：一种用于测试和燃烧半导体电路的方法和装置。该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。此外，ECA可以沉积在C4凸点或锡盖铅基上。该方法和装置的变化包括用ECA填充非导电插入件的通孔。可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

2. 发明授权

US06268739B1 Method and device for semiconductor testing using electrically conductive adhesives 失效
公开(公告)号：US06268739B1
公开(公告)日：2001-07-31
申请号：US09478678
申请日：2000-01-06
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.

3. 发明授权

US06288559B1 Semiconductor testing using electrically conductive adhesives 失效
标题翻译：使用导电胶的半导体测试
公开(公告)号：US06288559B1
公开(公告)日：2001-09-11
申请号：US09050820
申请日：1998-03-30
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.
摘要翻译：一种用于测试和燃烧半导体电路的方法和装置。该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。此外，ECA可以沉积在C4凸点或锡盖铅基上。该方法和装置的变化包括用ECA填充非导电插入件的通孔。可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

4. 发明授权

US06492071B1 Wafer scale encapsulation for integrated flip chip and surface mount technology assembly 失效
标题翻译：用于集成倒装芯片和表面贴装技术组装的晶圆级封装
公开(公告)号：US06492071B1
公开(公告)日：2002-12-10
申请号：US09670410
申请日：2000-09-26
申请人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
发明人： William E. Bernier , Mark V. Pierson , Ajit K. Trivedi
IPC分类号： G03F900
CPC分类号： H01L21/56 , H01L24/81 , H01L2224/274 , H01L2224/81801 , H01L2224/83191 , H01L2924/14 , H05K3/1225 , H01L2924/00
摘要： A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.
摘要翻译：提供了一种用于施加与焊料助焊剂组合的粘合剂制剂的混合物的装置和方法，使得可以用这种组合快速包封倒装芯片而不干扰后续的晶片加工步骤。还提供了以这样的方式设计的晶片模板，即分离各个芯片模具的锯切线不受制剂的接触。还提供了使用这种晶片模板的挤出筛选。

5. 发明授权

US07067916B2 Extension of fatigue life for C4 solder ball to chip connection 有权
公开(公告)号：US07067916B2
公开(公告)日：2006-06-27
申请号：US09885853
申请日：2001-06-20
申请人： William E. Bernier , Charles F. Carey , Eberhard B. Gramatzki , Thomas R. Homa , Eric A. Johnson , Pierre Langevin , Irving Memis , Son K. Tran , Robert F. White
发明人： William E. Bernier , Charles F. Carey , Eberhard B. Gramatzki , Thomas R. Homa , Eric A. Johnson , Pierre Langevin , Irving Memis , Son K. Tran , Robert F. White
IPC分类号： H01L23/48
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/81801 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01058 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/351 , H05K3/3436 , H01L2924/00
摘要： A method and structure for coupling a semiconductor substrate (e.g., a semiconductor chip) to an organic substrate (e.g., a chip carrier). The coupling interfaces a solder member (e.g., a solder ball) to both a conductive pad on the semiconductor substrate and a conductive pad on the organic substrate. Thermal strains on the solder member during thermal cycling may be reduced by having a surface area of the pad on the semiconductor substrate exceed a surface area of the pad on the organic substrate. Thermal strains on the solder member during thermal cycling may also be reduced by having a distance from a centerline of the solder member to a closest lateral edge of the semiconductor substrate exceed about 0.25 mm.

6. 发明授权

US06425772B1 Conductive adhesive having a palladium matrix interface between two metal surfaces 有权
标题翻译：在两个金属表面之间具有钯基体界面的导电粘合剂
公开(公告)号：US06425772B1
公开(公告)日：2002-07-30
申请号：US09911270
申请日：2001-07-23
申请人： William E. Bernier , Edward G. Bundga
发明人： William E. Bernier , Edward G. Bundga
IPC分类号： H01R458
CPC分类号： H01L24/83 , H01L24/29 , H01L2224/2919 , H01L2224/29499 , H01L2224/8319 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/0665 , H01L2924/0781 , H01L2924/14 , H01R4/04 , H01R12/52 , H05K3/321 , H05K2201/0129 , H05K2201/0218 , H05K2201/0245 , H05K2201/10977 , H05K2203/0307 , Y10T428/12569 , H01L2924/00
摘要： Forming an isotropic electrical connection and a mechanical bond between two articles having metal surfaces. The resulting bond is preferably between metal contact pads on a dielectric substrate and on an electronic device. The connection is provided by utilizing a conductive adhesive wherein the conduction is provided by metal particles which have exposed palladium thereon. The particles may be the metal palladium itself or it may be some other metal, such as silver, having palladium coated thereon. The particles typically are flakes with the palladium having an incipient dendritic form on the surface, i.e.; the palladium has a multi-pointed surface configuration that can grow into fully formed needle-like dendritic structures. The polymer preferably is conventional polyimide/siloxane which is a thermoplastic, i.e. upon heating softens and upon cooling sets, and upon reheating will soften and reflow.
摘要翻译：在具有金属表面的两个制品之间形成各向同性的电连接和机械结合。所得到的结合优选在电介质基底上的金属接触焊盘和电子器件之间。通过使用导电粘合剂提供连接，其中导电由其上具有暴露的钯的金属颗粒提供。颗粒可以是金属钯本身，或者它可以是一些其它金属，例如银，其上涂覆有钯。颗粒通常是表面上具有初始树枝状形式的钯的薄片，即，钯具有可以生长成完全形成的针状树枝状结构的多点表面构型。聚合物优选是热塑性的常规聚酰亚胺/硅氧烷，即加热时软化和冷却组合，并且在再加热时将软化和回流。

7. 发明授权

US08957531B2 Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity 有权
标题翻译：扁平层压板，对称测试结构和测量白色凸起敏感度的方法
公开(公告)号：US08957531B2
公开(公告)日：2015-02-17
申请号：US13277246
申请日：2011-10-20
申请人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
发明人： William E. Bernier , Timothy H. Daubenspeck , Virendra R. Jadhav , Valerie A. Oberson , David L. Questad
IPC分类号： H01L23/538 , H01L21/66 , H01L23/00 , G01N3/60 , G01N19/04
CPC分类号： H01L22/30 , B05D1/36 , G01N3/60 , G01N19/04 , G01N25/16 , G01N2203/0296 , G01N2203/0298 , H01L24/13 , H01L2224/131 , H01L2924/10253 , H01L2924/351 , H01L2924/014 , H01L2924/00
摘要： A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
摘要翻译：公开了一种对称的平板层压结构，用于使测试结构中的变量最小化，以实验测量白色凸起对CTE不匹配的敏感性。测试结构包括平板层压结构。使用测试结构的方法包括隔离多变量芯片连接问题的原因，其由翘曲不利地影响并量化翘曲的贡献本身在多变量芯片连接问题的形成中。

8. 发明授权

US08444043B1 Uniform solder reflow fixture 失效
标题翻译：均匀焊锡回流夹具
公开(公告)号：US08444043B1
公开(公告)日：2013-05-21
申请号：US13362228
申请日：2012-01-31
申请人： William E. Bernier , Marcus E. Interrante , Rajneesh Kumar , Chenzhou Lian , Janak G. Patel , Peter Slota, Jr.
发明人： William E. Bernier , Marcus E. Interrante , Rajneesh Kumar , Chenzhou Lian , Janak G. Patel , Peter Slota, Jr.
IPC分类号： B23K31/00 , B23K31/02
CPC分类号： H01L23/49816 , B23K1/0016 , B23K1/008 , B23K1/203 , B23K3/0623 , B23K2101/42 , H01L23/13 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L2224/13111 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/75101 , H01L2224/75252 , H01L2224/755 , H01L2224/75501 , H01L2224/81005 , H01L2224/81191 , H01L2224/81192 , H01L2224/81204 , H01L2224/81815 , H01L2225/06513 , H01L2924/10253 , H01L2924/1305 , H01L2924/15787 , H01L2924/351 , H01L2924/3511 , H01L2924/01047 , H01L2924/00012 , H01L2924/00014 , H01L2924/00
摘要： An array of solder balls is attached to solder pads of one of a first substrate and a second substrate. After aligning the array of solder balls relative to solder pads of the other of the first substrate and the second substrate, a thermal-mass-increasing fixture is placed on a surface of the second substrate to form an assembly of the first substrate, the second substrate, and the array of the solder balls therebetween, and the thermal-mass-increasing fixture. The thermal-mass-increasing fixture is in physical contact with at least a surface of a periphery of the second substrate. The thermal-mass-increasing fixture reduces the cool-down rate of peripheral solder balls after a reflow step, thereby increasing time for deformation of peripheral solder balls during the cool-down and reducing the mechanical stress on the solder balls after the cool-down.
摘要翻译：一组焊球附着到第一衬底和第二衬底之一的焊盘上。在相对于第一基板和第二基板中的另一个的焊盘对准焊球的阵列之后，将热质量增加的夹具放置在第二基板的表面上以形成第一基板的组件，第二基板基板以及它们之间的焊球的阵列，以及热质量增加夹具。热质量增加夹具与第二基板的周边的至少一个表面物理接触。热质量增加夹具降低了回流步骤后外围焊球的冷却速率，从而增加了冷却期间外围焊球变形的时间，并降低了冷却后焊锡球上的机械应力。

9. 发明授权

US07442878B2 Low stress conductive polymer bump 有权
标题翻译：低应力导电聚合物凸块
公开(公告)号：US07442878B2
公开(公告)日：2008-10-28
申请号：US11538823
申请日：2006-10-05
申请人： William E. Bernier , Marie S. Cole , Mukta G. Farooq , John U. Knickerbocker , Tasha E. Lopez , Roger A. Quon , David J. Welsh
发明人： William E. Bernier , Marie S. Cole , Mukta G. Farooq , John U. Knickerbocker , Tasha E. Lopez , Roger A. Quon , David J. Welsh
IPC分类号： H05K1/16
CPC分类号： H05K3/321 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/29 , H01L24/83 , H01L2224/0401 , H01L2224/05557 , H01L2224/13076 , H01L2224/13078 , H01L2224/1308 , H01L2224/131 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/13339 , H01L2224/13464 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/838 , H01L2924/00013 , H01L2924/01006 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/09701 , H01L2924/14 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H05K2201/0212 , H05K2201/0248 , H05K2201/0373 , H05K2201/1025 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/01026 , H01L2924/00015 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299
摘要： Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.
摘要翻译：公开了用于将集成电路器件连接到器件载体的层压（或非层叠）导电互连，其中导电互连包括交替的金属层和聚合物层。此外，聚合物可以包括枝晶，来自载体或器件的金属突起，和/或聚合物外部的胶束刷。聚合物层包括金属颗粒，并且交替的金属层和聚合物层形成立方体结构或圆柱形结构。

10. 发明授权

US06921015B2 Solder protective coating and fluxless joining of flip chip devices on laminates with plated solder 失效
标题翻译：倒装芯片器件的焊接保护涂层和无焊接接合在具有电镀焊料的层压板上
公开(公告)号：US06921015B2
公开(公告)日：2005-07-26
申请号：US10417690
申请日：2003-04-17
申请人： William E. Bernier , Donald W. Henderson , James Spalik , Isabelle Paquin
发明人： William E. Bernier , Donald W. Henderson , James Spalik , Isabelle Paquin
IPC分类号： B23K35/22 , C23C8/00 , C23C26/00 , H01L21/60 , H05K3/28 , H05K3/34 , B23K31/02
CPC分类号： H01L24/81 , B23K35/226 , C23C8/00 , C23C26/00 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/014 , H05K3/282 , H05K3/3457
摘要： A method for protecting tin oxide coated solder surfaces against further oxidation and a method for fluxless solder joining of such surfaces is provided.
摘要翻译：提供了一种用于保护氧化锡涂覆的焊料表面以防止进一步氧化的方法以及这种表面的无焊剂焊料接合的方法。

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