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1. 发明授权

US06573541B1 Charge coupled device with channel well 有权
标题翻译：电荷耦合器件通道良好
公开(公告)号：US06573541B1
公开(公告)日：2003-06-03
申请号：US09670595
申请日：2000-09-29
申请人： William A. Klaasen , Gary D. Pittman , Jed H. Rankin
发明人： William A. Klaasen , Gary D. Pittman , Jed H. Rankin
IPC分类号： H01L27148
CPC分类号： H01L29/76858 , H01L27/14887
摘要： A solid-state CCD device suitable for forming into arrays and for use with suitable hardware to form video image capture devices and methods for fabricating same are provided.
摘要翻译：提供了适合于形成阵列并与合适的硬件一起使用以形成视频图像捕获装置的固态CCD装置及其制造方法。

2. 发明授权

US06458630B1 Antifuse for use with low k dielectric foam insulators 失效
标题翻译：用于低k电介质泡沫绝缘子的防腐剂
公开(公告)号：US06458630B1
公开(公告)日：2002-10-01
申请号：US09417853
申请日：1999-10-14
申请人： Timothy H. Daubenspeck , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , Jed H. Rankin
发明人： Timothy H. Daubenspeck , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , Jed H. Rankin
IPC分类号： H01L2128
CPC分类号： H01L23/5254 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low k nanopore/nanofoam dielectric material adjacent the conductive line ends.
摘要翻译：用于半导体器件的可熔连接件包括在绝缘衬底的表面上的绝缘衬底和导电线对，导电线对具有间隔开的端部。聚合物设置在绝缘基板之上和导线对端之间。聚合物能够在暴露于能量束时从非导电状态改变为导电状态。优选地，聚合物包括聚酰亚胺，更优选聚合物/鎓盐混合物，最优选掺杂有三苯基鎓盐的聚苯胺聚合物。该连接可以进一步包括邻近导电线端部的低k纳米孔/纳米空间电介质材料。

3. 发明授权

US06496053B1 Corrosion insensitive fusible link using capacitance sensing for semiconductor devices 失效
标题翻译：使用半导体器件的电容感测的腐蚀不敏感的熔丝
公开(公告)号：US06496053B1
公开(公告)日：2002-12-17
申请号：US09416977
申请日：1999-10-13
申请人： Timothy Daubenspeck , Kurt R. Kimmel , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , W David Pricer , Jed H. Rankin
发明人： Timothy Daubenspeck , Kurt R. Kimmel , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , W David Pricer , Jed H. Rankin
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/5258 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： A structure and method for a programming device or a fuse includes a capacitive circuit having a capacitance which is alterable. The capacitive circuit can include a first capacitor, a fuse link connected to the first capacitor and a second capacitor connected to the fuse link, wherein removing a portion of the fuse link changes the capacitance.
摘要翻译：用于编程设备或熔丝的结构和方法包括具有可改变的电容的电容电路。电容电路可以包括第一电容器，连接到第一电容器的熔丝链和连接到熔丝链路的第二电容器，其中去除熔丝链的一部分改变电容。

4. 发明授权

US06835973B2 Antifuse for use with low &kgr; dielectric foam insulators 失效
标题翻译：用于低kappa电介质泡沫绝缘子的防腐剂
公开(公告)号：US06835973B2
公开(公告)日：2004-12-28
申请号：US10159573
申请日：2002-05-31
申请人： Timothy H. Daubenspeck , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , Jed H. Rankin
发明人： Timothy H. Daubenspeck , William A. Klaasen , William T. Motsiff , Rosemary A. Previti-Kelly , Jed H. Rankin
IPC分类号： H01L2710
CPC分类号： H01L23/5254 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A fusible link for a semiconductor device comprises an insulating substrate and a conductive line pair on the surface of the insulating substrate, with the conductive line pair having spaced ends. A polymer is disposed over the insulating substrate and between the conductive line pair ends. The polymer is capable of being changed from a non-conductive to a conductive state upon exposure to an energy beam. Preferably, the polymer comprises a polyimide, more preferably, a polymer/onium salt mixture, most preferably, a polyaniline polymer doped with a triphenylsufonium salt. The link may further comprise a low &kgr; nanopore/nanofoam dielectric material adjacent the conductive line ends.
摘要翻译：用于半导体器件的可熔连接件包括在绝缘衬底的表面上的绝缘衬底和导电线对，导电线对具有间隔开的端部。聚合物设置在绝缘基板之上和导线对端之间。聚合物能够在暴露于能量束时从非导电状态改变为导电状态。优选地，聚合物包括聚酰亚胺，更优选聚合物/鎓盐混合物，最优选掺杂有三苯基鎓盐的聚苯胺聚合物。该连接可以进一步包括邻近导线末端的低kappa纳米孔/纳米电流介电材料。

5. 发明授权

US07642813B2 Error correcting logic system 有权
标题翻译：错误校正逻辑系统
公开(公告)号：US07642813B2
公开(公告)日：2010-01-05
申请号：US11850857
申请日：2007-09-06
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

6. 发明授权

US06453431B1 System technique for detecting soft errors in statically coupled CMOS logic 失效
标题翻译：用于检测静态耦合CMOS逻辑中的软错误的系统技术
公开(公告)号：US06453431B1
公开(公告)日：2002-09-17
申请号：US09346509
申请日：1999-07-01
申请人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
IPC分类号： G06K504
CPC分类号： G11C5/005 , G06F11/00
摘要： Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.
摘要翻译：用于检测由于原子事件或其他非循环噪声源引起的逻辑电路中的错误瞬变的电路包括耦合到数据线的第一电路，用于感测在第一时间点（T1）的数据线上的第一信号，以及第二电路耦合到数据线，用于在第二时间点（T2）感测数据线上的第一信号，使得T1和T2之间的时间差足够小，使得第一信号在不存在的情况下仍然存在于数据线上的扰动事件，并且使得T1和T2之间的时间差足够大，使得任何这样的扰动事件被解决。耦合到第一和第二电路的比较电路比较第一和第二电路对第一信号的感测，并且响应于非比较而产生误差信号。

7. 发明授权

US06969859B2 Radiation detecting system 失效
标题翻译：辐射检测系统
公开(公告)号：US06969859B2
公开(公告)日：2005-11-29
申请号：US10249872
申请日：2003-05-14
申请人： William A. Klaasen , Edward J. Nowak , Norman J. Rohrer
发明人： William A. Klaasen , Edward J. Nowak , Norman J. Rohrer
IPC分类号： G01T1/15 , G01T1/17 , G01T1/24
CPC分类号： G01T1/17
摘要： A radiation detecting system including a radiation detecting section having one or more radiation detecting circuits and a circuit adjustment section for adjusting other circuitry to be protected. Radiation detecting circuits are provided to detect a pulse of radiation and/or a total radiation dose accumulation.
摘要翻译：一种辐射检测系统，包括具有一个或多个辐射检测电路的辐射检测部分和用于调节要被保护的其它电路的电路调整部分。提供辐射检测电路以检测辐射脉冲和/或总辐射剂量累积。

8. 发明授权

US06773952B2 Semiconductor chip structures with embedded thermal conductors and a thermal sink disposed over opposing substrate surfaces 失效
标题翻译：具有嵌入式热导体的半导体芯片结构和设置在相对基板表面上的散热器
公开(公告)号：US06773952B2
公开(公告)日：2004-08-10
申请号：US10243397
申请日：2002-09-12
申请人： Douglas S. Armbrust , William F. Clark , William A. Klaasen , William T. Motsiff , Timothy D. Sullivan
发明人： Douglas S. Armbrust , William F. Clark , William A. Klaasen , William T. Motsiff , Timothy D. Sullivan
IPC分类号： H01L2100
CPC分类号： H01L23/5222 , H01L23/3677 , H01L23/5329 , H01L2924/0002 , H01L2924/10158 , H01L2924/00
摘要： Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate. The thermal sink includes one or more thermally conductive via structures embedded within the substrate and aligned to thermally contact to the cooling posts disposed above the substrate.
摘要翻译：半导体芯片结构设置有用于从一个或多个导电电路构件去除热量的嵌入式热导体，其中电路构件形成在衬底上方的一个或多个电介质层上，每层具有低介电常数和低热导率。一个或多个冷却柱，例如多个导热塞，被选择性地设置在半导体芯片结构内邻近一个或多个导电构件并与其热耦合，使得由构件产生的热量被传送到冷却柱中并通过冷却柱转移到衬底和/或到半导体芯片结构的上表面。衬底的背面具有热耦合到其上并与衬底电隔离的散热器。散热器包括一个或多个热传导通孔结构，其嵌入衬底内并对准以与设置在衬底上方的冷却柱热接触。

9. 发明授权

US06515317B1 Sidewall charge-coupled device with multiple trenches in multiple wells 失效
标题翻译：侧壁电荷耦合器件，具有多个阱中的多个沟槽
公开(公告)号：US06515317B1
公开(公告)日：2003-02-04
申请号：US09670594
申请日：2000-09-29
申请人： Gregory Bazan , William A. Klaasen , Randy W. Mann
发明人： Gregory Bazan , William A. Klaasen , Randy W. Mann
IPC分类号： H01L2978
CPC分类号： H01L27/14887 , H01L27/1463 , H01L27/14806
摘要： Increased pixel density and increased sensitivity to blue light are provided in a charge couple device employing sidewall and surface gates.
摘要翻译：在使用侧壁和表面栅极的电荷耦合器件中提供增加的像素密度和增加对蓝光的灵敏度。

10. 发明授权

US07336102B2 Error correcting logic system 有权
公开(公告)号：US07336102B2
公开(公告)日：2008-02-26
申请号：US10710641
申请日：2004-07-27
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.

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