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1. 发明授权

US08234554B2 Soft error correction in sleeping processors 有权
标题翻译：睡眠处理器中的软错误校正
公开(公告)号：US08234554B2
公开(公告)日：2012-07-31
申请号：US12170462
申请日：2008-07-10
申请人： Kerry Bernstein , Norman J. Rohrer
发明人： Kerry Bernstein , Norman J. Rohrer
IPC分类号： H03M13/00
CPC分类号： H03M13/15 , G06F11/1008 , H03M13/098 , H03M13/13 , H03M13/1505 , H03M13/19
摘要： An error-correction code is generated on a line-by-line basis of the physical logic register and latch contents that store encoded words within a processor just before the processor is put into sleep mode, and later-generated syndrome bits are checked for any soft errors when the processor wakes back up, e.g., as part of the power-up sequence.
摘要翻译：在处理器进入睡眠模式之前，将物理逻辑寄存器和锁存内容逐行生成在处理器内的处理器内，生成错误校正码，并检查后来生成的校验码位处理器唤醒时出现软错误，例如作为上电顺序的一部分。

2. 发明申请

US20120066657A1 METHOD OF DESIGNING AN INTEGRATED CIRCUIT BASED ON A COMBINATION OF MANUFACTURABILITY, TEST COVERAGE AND, OPTIONALLY, DIAGNOSTIC COVERAGE 有权
标题翻译：基于可制造性，测试覆盖和可选择的诊断覆盖的组合设计集成电路的方法
公开(公告)号：US20120066657A1
公开(公告)日：2012-03-15
申请号：US12880228
申请日：2010-09-13
申请人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
发明人： Kerry Bernstein , James A. Culp , Leah M.P. Pastel , Kirk D. Peterson , Norman J. Rohrer
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045 , G06F2217/12 , Y02P90/265
摘要： Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.
摘要翻译：披露是基于可制造性，测试覆盖和任选的诊断覆盖的组合的集成电路设计方法的实施例。根据测试覆盖范围，可以对集成电路布局的可制造性（DFM）进行设计修改。或者，可以根据DFM修改建立集成电路的测试覆盖。或者，可以执行迭代处理，其中根据测试覆盖进行DFM对集成电路的布局的修改，然后根据DFM修改来改变测试覆盖。或者，DFM可以根据测试覆盖范围和诊断覆盖范围对集成电路布局进行修改。在任何情况下，在进行DFM修改和建立测试覆盖之后，可以识别和标记集成电路中的任何未修改和未测试的节点（以及可选地，任何未修改和不可判定的测试节点）以便随后的在线检查。

3. 发明授权

US07996810B2 System and method for designing a low leakage monotonic CMOS logic circuit 有权
标题翻译：用于设计低泄漏单调CMOS逻辑电路的系统和方法
公开(公告)号：US07996810B2
公开(公告)日：2011-08-09
申请号：US12103038
申请日：2008-04-15
申请人： Kerry Bernstein , Norman J. Rohrer
发明人： Kerry Bernstein , Norman J. Rohrer
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , H03K19/0016 , H03K19/0948
摘要： A computer system for designing a low leakage monotonic CMOS logic circuit. The system performing the computer implements steps of: (a) specifying a reference PFET having its threshold voltage and its gate dielectric thickness and a reference NFET having its threshold voltage and its gate dielectric thickness; (b) synthesizing a schematic circuit design with standard design elements, the standard design elements including one or more reference PFETS and one or more reference NFETs; (c) analyzing one or more circuits for logic stages having predominantly high input logic states or predominantly low input logic states; (d) selecting one or more logic stages determined to have predominantly high input logic states or predominantly low input logic states; and (e) replacing the standard design elements of the selected logic stages with reduced current leakage elements.
摘要翻译：一种用于设计低泄漏单调CMOS逻辑电路的计算机系统。执行计算机的系统实现以下步骤：（a）指定具有其阈值电压及其栅介质厚度的参考PFET和具有其阈值电压及其栅介质厚度的参考NFET; （b）用标准设计元件合成示意电路设计，标准设计元件包括一个或多个参考PFET和一个或多个参考NFET; （c）分析具有主要为高输入逻辑状态或主要为低输入逻辑状态的逻辑级的一个或多个电路; （d）选择确定为具有主要高输入逻辑状态或主要为低输入逻辑状态的一个或多个逻辑级; 和（e）用减少的电流泄漏元件代替所选逻辑级的标准设计元件。

4. 发明授权

US07757137B2 Method and apparatus for on-the-fly minimum power state transition 失效
标题翻译：用于实时最小功率状态转换的方法和装置
公开(公告)号：US07757137B2
公开(公告)日：2010-07-13
申请号：US11691856
申请日：2007-03-27
申请人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
发明人： Alberto Garcia Ortiz , Cedric Lichtenau , Norman J. Rohrer
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318575
摘要： The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation. The switching occurs in only one clock cycle.
摘要翻译：本发明包括用于LSSD或GSD IC操作的新型扫描链结构。扫描链结构包括在扫描模式操作中，在初始化模式和低泄漏状态下，被配置为在正常模式操作中操作第一触发器（L1）的第一触发器（L1）和第二触发器（L2）功率模式操作，其中锁存器的长扫描链内的每个触发器包括布置用于正常模式操作的数据输入，数据输出，时钟输入，扫描输入和扫描输出输出。缓冲电路电连接在第二触发器（L2）的扫出输出端和第一触发器（L1）的扫描输入端之间用于扫描链中的下一个锁存器，缓冲电路包括一个控制元件，其控制第一触发器（L1）的扫描模式或低功率泄漏模式的操作。在从低功率泄漏模式退出时，第一触发器（L1）被设置为数据输出值，该值是在正常模式操作期间初始化时被设置为相同的值。开关仅在一个时钟周期内发生。

5. 发明授权

US07701035B2 Laser fuse structures for high power applications 失效
标题翻译：用于大功率应用的激光熔丝结构
公开(公告)号：US07701035B2
公开(公告)日：2010-04-20
申请号：US11164640
申请日：2005-11-30
申请人： Stephen E. Greco , Erik L. Hedberg , Dae-Young Jung , Paul S. McLaughlin , Christopher D. Muzzy , Norman J. Rohrer , Jean E. Wynne
发明人： Stephen E. Greco , Erik L. Hedberg , Dae-Young Jung , Paul S. McLaughlin , Christopher D. Muzzy , Norman J. Rohrer , Jean E. Wynne
IPC分类号： H01L23/525 , H01L21/768
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a laser fuse structure for high power applications. Specifically, the laser fuse structure of the present invention comprises first and second conductive supporting elements (12a, 12b), at least one conductive fusible link (14), first and second connection elements (20a, 20b), and first and second metal lines (22a, 22b). The conductive supporting elements (12a, 12b), the conductive fusible link (14), and the metal lines (22a, 22b) are located at a first metal level (3), while the connect elements (20a, 20b) are located at a second, different metal level (4) and are connected to the conductive supporting elements (12a, 12b) and the metal lines (22a, 22b) by conductive via stacks (18a, 18b, 23a, 23b) that extend between the first and second metal levels (3, 4).
摘要翻译：本发明涉及一种用于大功率应用的激光熔丝结构。具体地，本发明的激光熔丝结构包括第一和第二导电支撑元件（12a，12b），至少一个导电熔丝（14），第一和第二连接元件（20a，20b）以及第一和第二金属线（22a，22b）。导电支撑元件（12a，12b），导电熔丝（14）和金属线（22a，22b）位于第一金属层（3）处，而连接元件（20a，20b）位于第二不同的金属层（4），并且通过在第一和第二金属层之间延伸的导电通孔叠层（18a，18b，23a，23b）连接到导电支撑元件（12a，12b）和金属线（22a，22b）第二金属含量（3,4）。

6. 发明授权

US07642813B2 Error correcting logic system 有权
标题翻译：错误校正逻辑系统
公开(公告)号：US07642813B2
公开(公告)日：2010-01-05
申请号：US11850857
申请日：2007-09-06
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/20 , H03K19/094 , H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

7. 发明授权

US07602635B2 Structure for a configurable SRAM system and method 有权
标题翻译：可配置SRAM系统和方法的结构
公开(公告)号：US07602635B2
公开(公告)日：2009-10-13
申请号：US11947092
申请日：2007-11-29
申请人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
发明人： Christopher J. Gonzalez , Vinod Ramadurai , Norman J. Rohrer
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , G11C11/413
摘要： A design structure for a static random access memory (SRAM) circuit includes first SRAM cell and a second SRAM cell that are configured to operate in a shared mode and/or an independent mode. In one example, a shared mode includes the sharing of a memory node of a first SRAM cell. In another example, an independent mode includes isolating a first SRAM cell from a second SRAM cell such that they operate independently.
摘要翻译：静态随机存取存储器（SRAM）电路的设计结构包括被配置为在共享模式和/或独立模式下操作的第一SRAM单元和第二SRAM单元。在一个示例中，共享模式包括共享第一SRAM单元的存储器节点。在另一示例中，独立模式包括将第一SRAM单元与第二SRAM单元隔离开，使得它们独立工作。

8. 发明授权

US07129545B2 Charge modulation network for multiple power domains for silicon-on-insulator technology 失效
公开(公告)号：US07129545B2
公开(公告)日：2006-10-31
申请号：US10906563
申请日：2005-02-24
申请人： David A. Cain , Jeffrey P. Gambino , Norman J. Rohrer , Daryl M. Seitzer , Steven H. Voldman
发明人： David A. Cain , Jeffrey P. Gambino , Norman J. Rohrer , Daryl M. Seitzer , Steven H. Voldman
IPC分类号： H02H9/00
CPC分类号： H01L27/0251
摘要： An SOI integrated circuit includes ESD protection on an SOI chip. A first power domain and a second power domain are provided in the SOI chip. In one embodiment, a charge modulation network in the SOI chip between the first power domain and the second power domain mitigates accumulation of electrical charge in an electrically isolated region of the SOI chip. In another embodiment, an ESD protection device in the SOI chip electrically connects the first power domain and the second power domain via a low metal layer to provide a discharge path for accumulated charge.

9. 发明授权

US06455336B1 Power reduction method and design technique for burn-in 失效
标题翻译：降耗方法和烧录设计技术
公开(公告)号：US06455336B1
公开(公告)日：2002-09-24
申请号：US09682381
申请日：2001-08-27
申请人： Zachary E. Berndlmaier , Mark R. Bilak , Norman J. Rohrer
发明人： Zachary E. Berndlmaier , Mark R. Bilak , Norman J. Rohrer
IPC分类号： H01L2166
CPC分类号： G01R31/2879 , G01R31/2856
摘要： A design and burn-in technique that effectively reduces power consumption during burn-in for devices with high power consumption as a result of shrinking voltages, high instantaneous current, subthreshold leakage and high currents at stress conditions. Three methods of reducing power consumption during burn-in are disclosed in detail: (1) completely separate power grids, (2) isolated grids during burn-in, and (3) isolated grids for MTCMOS used during burn-in. Each technique provides a method of segmenting the power supply of a chip and controlling which segment of the chip is stressed based on which segment is ‘powered on’. Those segments not being stressed are ‘shutoff’ so as to reduce power consumption.
摘要翻译：一种设计和老化技术，可以有效降低由于电压缩减，高瞬时电流，亚阈值泄漏和应力条件下的高电流而导致高功耗器件老化过程中的功耗。详细介绍了三种降低老化过程中功耗的方法：（1）完全分离电网，（2）老化期间的隔离栅格，（3）老化过程中使用的MTCMOS隔离网格。每种技术提供了一种分割芯片的电源的方法，并且基于哪个部分被“通电”来控制芯片的哪个片段被应力，那些不受应力的片段是“关闭”，以便降低功耗。

10. 发明申请

US20090002015A1 ERROR CORRECTING LOGIC SYSTEM 有权
标题翻译：错误修正逻辑系统
公开(公告)号：US20090002015A1
公开(公告)日：2009-01-01
申请号：US11850857
申请日：2007-09-06
申请人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
发明人： Kerry Bernstein , Philip G. Emma , John A. Fifield , Paul D. Kartschoke , William A. Klaasen , Norman J. Rohrer
IPC分类号： H03K19/003
CPC分类号： H03K19/007
摘要： The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.
摘要翻译：本发明包括纠错逻辑系统，其允许仅使用一个冗余单元来硬化关键电路并且不损失电路性能。该系统提供互连门，其抑制馈送到互连门的至少两个冗余动态逻辑门之一的故障。该系统适用于动态或静态逻辑系统。该系统防止故障传播，不仅解决软错误，而且还会引起噪声引起的错误。此外，提供了在设计过程中使用的机器可读介质中体现的设计结构，并且包括这种纠错逻辑系统。

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