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1. 发明授权

US06636993B1 System and method for automatic deskew across a high speed, parallel interconnection 有权
标题翻译：用于跨高速并行互连的自动校正的系统和方法
公开(公告)号：US06636993B1
公开(公告)日：2003-10-21
申请号：US09249935
申请日：1999-02-12
申请人： Yoichi Koyanagi , Richard L. Schober , Raghu Sastry , Hirotaka Tamura
发明人： Yoichi Koyanagi , Richard L. Schober , Raghu Sastry , Hirotaka Tamura
IPC分类号： G06K504
CPC分类号： G06F5/06 , H04L25/14
摘要： A method and system performs automatic deskew tuning and alignment across high-speed, parallel interconnections in a high performance digital system to compensate for inter-bit skew. Rather than using a VDL, digital elements such as registers and multiplexers are used for performing the automatic deskew tuning and alignment procedure. The result is a simpler, more robust deskew system capable of operating over a wider range of input values with greater accuracy and over a broader range of temperatures. In addition, the method and apparatus performs a one to four unfolding of the signal on each interconnection. The system includes a deskew controller and a plurality deskew subsystems. The deskew controller computes the amount of delay needed to correct the skew on each interconnection and feeds a different (or appropriate) delay value to each deskew subsystem located at the receiving end of each interconnection.
摘要翻译：一种方法和系统在高性能数字系统的高速，并行互连中进行自动偏移校正和对准，以补偿位间偏移。使用数字元件（如寄存器和多路复用器）而不是使用VDL来执行自动偏移校正和校准过程。结果是一个更简单，更强大的偏移校正系统，能够在更广泛的输入值范围内运行，具有更高的精度和更宽的温度范围。此外，该方法和装置在每个互连上执行一至四次的信号展开。该系统包括一个歪斜控制器和多个歪斜系统子系统。歪斜控制器计算校正每个互连件上的偏斜所需的延迟量，并将不同（或适当的）延迟值馈送到位于每个互连接收端的每个歪斜校正子系统。

2. 发明授权

US06688524B1 Method for reconstructing a bar code through consecutive scans 有权
标题翻译：通过连续扫描重建条形码的方法
公开(公告)号：US06688524B1
公开(公告)日：2004-02-10
申请号：US09631963
申请日：2000-08-03
申请人： Marco Bottazzi , Elena Brunelli , Rinaldo Zocca
发明人： Marco Bottazzi , Elena Brunelli , Rinaldo Zocca
IPC分类号： G06K504
CPC分类号： G06K7/1465 , G06K7/14
摘要： The method for reconstructing a bar code through consecutive scans comprises the following steps: a) carrying out at least one scan of the bar code; b) determining a reconstructed wave form representative of the at least one scan; c) carrying out an actual scan of the bar code; d) determining an actual wave form representative of the actual scan; e) aligning the reconstructed and actual wave forms; and f) combining the aligned wave forms by updating the reconstructed wave form with the actual wave form. The method can directly operate on the photo-sensor signal before carrying out any digitization of it.
摘要翻译：通过连续扫描重建条形码的方法包括以下步骤：a）对条形码进行至少一次扫描; b）确定表示所述至少一个扫描的重构波形; c）对条码进行实际扫描; d）确定表示实际扫描的实际波形; e）对准重建和实际波形; 以及f）通过用实际波形更新重构的波形来组合对准的波形。该方法可以在进行任何数字化之前直接对光电传感器信号进行操作。

3. 发明授权

US06405924B1 Inventory control system and method 有权
标题翻译：库存控制系统和方法
公开(公告)号：US06405924B1
公开(公告)日：2002-06-18
申请号：US09493604
申请日：2000-01-28
申请人： Pragnesh S. Shah
发明人： Pragnesh S. Shah
IPC分类号： G06K504
CPC分类号： G06K17/00 , G06K2017/0051
摘要： An inventory use recording system and method having an optical reader module for scanning component bar codes of an inventory batch having serialized bar codes, a controller module for storing at least a first tag representation and a second tag representation where the second tag representation is a tag representation from a next available component in the inventory batch after a predetermined time period where a quantity of the components have been withdrawn from the inventory batch, and a display module for displaying inventory use.
摘要翻译：一种库存使用记录系统和方法，具有用于扫描具有串行化条形码的库存批次的组件条形码的光学读取器模块，用于存储至少第一标签表示的控制器模块和第二标签表示是标签的第二标签表示在从库存批次中取出数量的组件的预定时间段之后的库存批次中的下一个可用组件的表示，以及用于显示库存使用的显示模块。

4. 发明授权

US06260762B1 Method for coding mailing items 失效
标题翻译：邮件编码方法
公开(公告)号：US06260762B1
公开(公告)日：2001-07-17
申请号：US09308413
申请日：1999-07-14
申请人： Boris Lohmann
发明人： Boris Lohmann
IPC分类号： G06K504
CPC分类号： G07B17/00508 , B07C3/18 , G07B2017/0058 , G07B2017/00588 , G07B2017/00685
摘要： A method for coding mailing items, in which a determination of the surface available for applying an unambiguous code to arriving mailing items is conducted and an application of the unambiguous code with a number of code signs that is adapted to the respectively determined surface available for coding is performed.
摘要翻译：一种用于编码邮件的方法，其中进行可用于向到达邮寄项目应用明确代码的表面的确定，以及具有适合于分别确定的可用于编码的表面的多个代码符号的明确代码的应用被执行。

5. 发明授权

US06701466B1 Serial data communication receiver having adaptively minimized capture latch offset voltage 失效
标题翻译：串行数据通信接收机具有自适应地最小化捕获锁存器失调电压
公开(公告)号：US06701466B1
公开(公告)日：2004-03-02
申请号：US09677350
申请日：2000-10-02
申请人： Alan S. Fiedler
发明人： Alan S. Fiedler
IPC分类号： G06K504
CPC分类号： H03L7/081 , H03L7/0891 , H03L7/091 , H03L7/0995 , H04L7/0037 , H04L7/033
摘要： A serial data communication receiver includes a serial data input and first and second sets of data capture latches, which are coupled to the serial data input and have first and second recovered data outputs, respectively. One of the sets is designated as a master set and the other a slave set. Each data capture latch has a respective independently adjustable offset voltage. An offset adjustment control circuit varies the respective offset voltage over a range of offset voltage values for each of the data capture latches in the slave set while comparing the first and second recovered data outputs to produce an error output. The control circuit then sets each of the respective offset voltages in the slave set to one of the offset voltage values based on the error output.
摘要翻译：串行数据通信接收机包括串行数据输入以及耦合到串行数据输入的第一和第二组数据捕获锁存器，并分别具有第一和第二恢复数据输出。其中一个集合被指定为主集，另一个被指定为从集。每个数据捕获锁存器具有各自独立可调的失调电压。偏移调整控制电路在比较第一和第二恢复数据输出以产生误差输出时，在从属组中的每个数据捕获锁存器的偏移电压值的范围上改变各个偏移电压。然后，控制电路基于错误输出将从设定中的各偏移电压中的每一个设置为偏移电压值之一。

6. 发明授权

US06668342B2 Apparatus for a radiation hardened clock splitter 有权
标题翻译：辐射硬化时钟分离器的装置
公开(公告)号：US06668342B2
公开(公告)日：2003-12-23
申请号：US09838131
申请日：2001-04-20
申请人： Neil E. Wood , Eric J. Hatch
发明人： Neil E. Wood , Eric J. Hatch
IPC分类号： G06K504
CPC分类号： G06F1/10 , G06F1/04 , G06F1/06 , H03K5/1515
摘要： A clock splitter circuit provides a radiation hardened pair of adjustably non-overlapping complementary clocks. The circuit includes a pair of clock inverter legs. Each clock inverter leg can include an and-or-inverter (AOI) circuit having a first input coupled to an overlap_en signal, a second input coupled to an inverted overlap_en signal, a third input coupled to an inverted first clock input signal, and a fourth input coupled to an second clock input signal that is substantially 180 degrees out of phase with the first clock input signal. Each clock inverter leg can further include an asymmetric variable delay (AVD) circuit having an input coupled to an output of the first AOI circuit and an input coupled to a waitr_signal that can be used to delay and adjust breadth of non-overlap. Each leg can further include a tri-state inverter circuit having a first input coupled to an output of the AVD circuit, and a second input coupled to the inverted first clock input signal. Each leg can further include an inverter having an input coupled to an output of the tri-state inverter circuit, and an output coupled to a first clock output signal.
摘要翻译：时钟分配器电路提供辐射硬化对可调整地不重叠的互补时钟。该电路包括一对时钟反相器支脚。每个时钟反相器支路可以包括具有耦合到重叠信号的第一输入和耦合到反向重叠信号的第二输入的第一输入和耦合到反相第一时钟输入信号的第三输入的反相器（AOI）电路，第四输入耦合到与第一时钟输入信号基本上为180度异相的第二时钟输入信号。每个时钟反相器支路还可以包括具有耦合到第一AOI电路的输出的输入的非对称可变延迟（AVD）电路和耦合到等待信号的输入，该信号可用于延迟和调整不重叠的宽度。每个支路还可以包括三态逆变器电路，其具有耦合到AVD电路的输出的第一输入和耦合到反相的第一时钟输入信号的第二输入。每个支腿还可以包括具有耦合到三态反相器电路的输出的输入的反相器和耦合到第一时钟输出信号的输出。

7. 发明授权

US06332574B1 Method of reading bar code 有权
标题翻译：阅读条码的方法
公开(公告)号：US06332574B1
公开(公告)日：2001-12-25
申请号：US09438847
申请日：1999-11-12
申请人： Hisashi Shigekusa , Masami Tanaka , Tadao Oshima
发明人： Hisashi Shigekusa , Masami Tanaka , Tadao Oshima
IPC分类号： G06K504
CPC分类号： G06K7/1092 , G06K7/10722 , G06K7/1093 , G06K7/14 , G06K7/1443 , G06K7/1491
摘要： A method of reading a bar code having guard bars at both sides thereof without fail even if the bar code image is highly distorted. An image region taken in by a CCD camera is scanned in horizontal and/or vertical directions to find out a first guard bar in the bar code. Then, a first scanning line for reading the bar code is set in a direction perpendicular to the first guard bar. The bar code is scanned along the first scanning line. If the first scanning line goes out of the bar code region, the first scanning line is traced back to a bar which is last read. Another scanning line starting from the last read bar and extending perpendicularly thereto is set to read the rest of the bar code. This process is repeated until the second guard bar is detected and a whole bar code is completely read. The first scanning line may be set, so that it only reads a predetermined number of bars and the rest of the bar code is read by new scanning lines starting from the last read bar. Alternatively, the bar code region is searched by preliminarily scanning the image region divided into plural rectangular sections. The bar code region is determined based on the number of brightness changes in each divided section. The first guard bar in the bar code can be easily found in this manner.
摘要翻译：即使条形码图像高度失真，也不会失败地读取其两侧具有保护条的条形码的方法。通过CCD摄像机拍摄的图像区域在水平和/或垂直方向上扫描，以便在条形码中找到第一保护条。然后，在与第一保护条垂直的方向上设置用于读取条形码的第一扫描线。沿着第一条扫描线扫描条形码。如果第一条扫描线超出条形码区域，则第一条扫描线将被追溯到最后读取的条形。从最后一个读取条开始并垂直延伸的另一个扫描线被设置为读取条形码的其余部分。重复该过程，直到检测到第二保护条，并且完全读取整个条形码。可以设置第一扫描线，使得其仅读取预定数量的条，并且从最后读取条开始，通过新的扫描线读取其余条形码。或者，通过预先扫描分割成多个矩形部分的图像区域来搜索条形码区域。根据每个划分的部分中的亮度变化的数量来确定条形码区域。条形码中的第一个保护条可以轻松地以这种方式找到。

8. 发明授权

US06327678B1 Skew adjusting method in IC testing apparatus and pseudo device for use in the method 有权
标题翻译： IC测试装置中的倾斜调整方法和该方法中使用的伪装置
公开(公告)号：US06327678B1
公开(公告)日：2001-12-04
申请号：US09286358
申请日：1999-04-05
申请人： Hiroyuki Nagai
发明人： Hiroyuki Nagai
IPC分类号： G06K504
CPC分类号： G01R31/31725 , G01R31/3191
摘要： There are provided a skew adjusting method capable of accurately conducting a skew adjustment in an IC testing apparatus comprising a plurality of pin cards and an IC socket, and a pseudo device for use in the skew adjusting method. Any one 11N of the pin cards 11A to 11N which are connected to terminals of the IC socket respectively, is defined as a reference pin card. A plurality of pseudo devices 12 are prepared, each of which electrically connects to the reference pin card 11N one of the remaining pin cards through the IC socket when that pseudo device is mounted thereon. The pseudo devices are sequentially mounted on the IC socket to connect all drivers DR of the remaining pin cards one by one to a voltage comparator CPN of the reference pin card. And variable delay circuits DRY1 and DRY2 of each pin card are adjusted so that a delay in phase of the driver of each pin card may coincide with a delay in phase defined as a reference.
摘要翻译：提供了一种能够在包括多个针卡和IC插座的IC测试装置中精确地进行偏斜调整的偏斜调整方法，以及用于偏斜调整方法的伪装置。分别连接到IC插座的端子的针卡11A至11N中的任何一个11N被定义为参考针卡。准备了多个伪装置12，当伪装置安装在其上时，每个伪装置12通过IC插座将其中的一个电连接到基准销卡11N。伪器件依次安装在IC插座上，将剩余引脚卡的所有驱动器DR逐个连接到参考引脚卡的电压比较器CPN。并且每个针卡的可变延迟电路DRY1和DRY2被调节，使得每个针卡的驱动器的相位延迟可与定义为参考的相位延迟重合。

9. 发明授权

US06643820B2 Signal processing circuit with timing recovery PLL 有权
标题翻译：具有定时恢复PLL的信号处理电路
公开(公告)号：US06643820B2
公开(公告)日：2003-11-04
申请号：US09430100
申请日：1999-10-29
申请人： Tsuyoshi Tomita
发明人： Tsuyoshi Tomita
IPC分类号： G06K504
CPC分类号： G11B20/1403
摘要： A signal processing circuit for processing a read signal corresponding to data read from a recording medium, such as a magnetic disc. The signal processing circuit detects a preamble data signal of the read signal. A decision feedback equalizer (DFE) generates a computation read signal by performing a predetermined computation on the read signal in accordance with a clock signal. The DFE generates first code data using the computation read signal. A code data generating circuit connected to the DFE compares the computation read signal with a first reference signal and generates second code data, which corresponds to the preamble data signal. A phase error detection circuit detects a phase error between the clock signal and the read signal using one of the first and second code data. A timing recovery PLL is connected to the phase error detection circuit and uses the detected phase error to generate the clock signal such that the phase of the clock signal matches the phase of the preamble data signal.
摘要翻译：一种用于处理对应于从诸如磁盘的记录介质读取的数据的读取信号的信号处理电路。信号处理电路检测读信号的前同步码数据信号。判决反馈均衡器（DFE）通过根据时钟信号对读取信号执行预定的计算来生成计算读取信号。 DFE使用计算读取信号产生第一代码数据。连接到DFE的代码数据生成电路将计算读取信号与第一参考信号进行比较，并产生对应于前导码数据信号的第二代码数据。相位误差检测电路使用第一和第二代码数据之一检测时钟信号和读取信号之间的相位误差。定时恢复PLL连接到相位误差检测电路，并使用检测到的相位误差来产生时钟信号，使得时钟信号的相位与前导码数据信号的相位匹配。

10. 发明授权

US06477668B1 Signal generation circuit of semiconductor testing apparatus 失效
标题翻译：半导体测试仪的信号发生电路
公开(公告)号：US06477668B1
公开(公告)日：2002-11-05
申请号：US09576095
申请日：2000-05-22
申请人： Kiyoshi Ito
发明人： Kiyoshi Ito
IPC分类号： G06K504
CPC分类号： G01R31/31928 , G01R31/31926 , G01R31/31937
摘要： A signal is generated according to the waveform information designated by a program and outputted by the format channels 1 and 2. Skew correction circuits 51 to 54 are provided corresponding to the format channel 1 and 2, and the signal outputted from the corresponding format channel is used as the reference, and the skew of the signal outputted from the other format channel is corrected. Logical add circuits 61 to 64 are provided corresponding to the skew correction circuits 51 to 54, and compose the signal from the corresponding skew correction circuit and the signal from the format channel to which this skew correction circuit corresponds.
摘要翻译：根据由程序指定并由格式通道1和2输出的波形信息产生信号。对应于格式通道1和2提供偏斜校正电路51至54，并且从相应的格式通道输出的信号是用作参考，并且校正从另一格式信道输出的信号的偏斜。对应于偏斜校正电路51至54提供逻辑加法电路61至64，并且构成来自对应的歪斜校正电路的信号和来自该歪斜校正电路对应的格式通道的信号。

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