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1. 发明申请

US20080246057A1 Silicon layer for stopping dislocation propagation 有权
标题翻译：用于阻止位错传播的硅层
公开(公告)号：US20080246057A1
公开(公告)日：2008-10-09
申请号：US11732889
申请日：2007-04-05
申请人： Hsien-Hsin Lin , Weng Chang , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Ming-Hua Yu
发明人： Hsien-Hsin Lin , Weng Chang , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Ming-Hua Yu
IPC分类号： H01L29/78
CPC分类号： H01L29/66477 , H01L21/02532 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
摘要翻译：提供一种复合半导体结构及其形成方法。复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。第一和第二含硅化合物层具有比硅层低的硅浓度。复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

2. 发明授权

US07119404B2 High performance strained channel MOSFETs by coupled stress effects 有权
标题翻译：高性能应变通道MOSFET通过耦合应力效应
公开(公告)号：US07119404B2
公开(公告)日：2006-10-10
申请号：US10849689
申请日：2004-05-19
申请人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
发明人： Cheng-Hung Chang , Weng Chang , Chu-Yun Fu
IPC分类号： H01L31/62 , H01L21/8238
CPC分类号： H01L29/7845 , H01L21/823807 , H01L21/823828 , H01L21/823878 , H01L29/7842 , H01L29/7843 , H01L29/7846
摘要： Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strained shallow trench isolation regions in the semiconductor substrate; forming PMOS and NMOS devices on the semiconductor substrate including doped source and drain regions; forming a tensile strained contact etching stop layer (CESL) over the PMOS and NMOS devices; and, forming a tensile strained dielectric insulating layer over the CESL layer.
摘要翻译：包括PMOS和NMOS器件对的应变沟道晶体管，以改善NMOS器件性能而不会使PMOS器件性能基本上降低，并且用于形成PMOS器件性能的方法，所述方法包括提供半导体衬底; 在半导体衬底中形成应变浅沟槽隔离区; 在包括掺杂源极和漏极区域的半导体衬底上形成PMOS和NMOS器件; 在PMOS和NMOS器件上形成拉伸应变接触蚀刻停止层（CESL）; 并在CESL层上形成拉伸应变电介质绝缘层。

3. 发明申请

US20050236694A1 Silicon oxycarbide and silicon carbonitride based materials for MOS devices 有权
标题翻译：用于MOS器件的碳氧化硅和碳氮化硅基材料
公开(公告)号：US20050236694A1
公开(公告)日：2005-10-27
申请号：US10895514
申请日：2004-07-21
申请人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
发明人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
IPC分类号： H01L21/31 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/768 , H01L23/31 , H01L23/58 , H01L29/49
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/3192 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.
摘要翻译：在优选实施例中，在基板上形成栅极电介质和电极。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。间隔物优选由SiCO基材料或SiCN基材料形成。然后形成源极和漏极。在源极/漏极区域和间隔物上形成接触蚀刻停止层（CES）层。 CES层优选由SiCO基材料或SiCN基材料形成。然后在CES层上形成级间介质（ILD）。

4. 发明授权

US06828245B2 Method of improving an etching profile in dual damascene etching 失效
标题翻译：在双镶嵌蚀刻中改善蚀刻轮廓的方法
公开(公告)号：US06828245B2
公开(公告)日：2004-12-07
申请号：US10087673
申请日：2002-03-02
申请人： Weng Chang
发明人： Weng Chang
IPC分类号： H01L21302
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76804 , H01L21/76831 , H01L21/76865
摘要： A plasma etching method for improving an etching profile including providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device; providing a patterned photoresist layer exposing an uppermost layer of the substrate for anisotropically plasma etching a first opening; anisotropically plasma etching through a thickness of at least a portion of the substrate to form the first opening; blanket depositing an etching stop liner to cover at least a portion of the sidewalls of the first opening; patterning according to a photolithographic process for etching a second opening at least partially overlying and encompassing the first opening; and, anisotropically plasma etching through at least another portion of the thickness of the substrate including the first opening to form a second opening at least partially overlying a remaining portion of the first opening.
摘要翻译：一种用于改进蚀刻轮廓的等离子体蚀刻方法，包括在多层半导体器件中提供包括含有绝缘层的氧化物的衬底; 提供曝光所述衬底的最上层的图案化光致抗蚀剂层，用于各向异性等离子体蚀刻第一开口; 通过基板的至少一部分的厚度进行各向异性等离子体蚀刻以形成第一开口; 毯式地沉积蚀刻停止衬套以覆盖第一开口的侧壁的至少一部分; 根据光刻工艺图案化，用于蚀刻至少部分地覆盖并包围第一开口的第二开口; 以及通过包括第一开口的基板的厚度的至少另一部分进行各向异性等离子体蚀刻，以形成至少部分地覆盖第一开口的剩余部分的第二开口。

5. 发明授权

US06383935B1 Method of reducing dishing and erosion using a sacrificial layer 有权
标题翻译：使用牺牲层减少凹陷和侵蚀的方法
公开(公告)号：US06383935B1
公开(公告)日：2002-05-07
申请号：US09687162
申请日：2000-10-16
申请人： Cheng Chung Lin , Chen Hua Yu , Tsu Shih , Weng Chang
发明人： Cheng Chung Lin , Chen Hua Yu , Tsu Shih , Weng Chang
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.
摘要翻译：已知化学机械抛光（CMP）在平坦化表面包括部分填充有金属的宽沟槽时引起凹陷。首先用在CMP下的抛光速率与沟槽中的金属相似的材料填充沟槽已经克服了这个问题。旋转涂层用于此，使得只有沟槽被填充。在CMP之后，除去该材料的任何残余物，留下已经被平坦化到预期程度的表面，而不引入显着的凹陷并且金属的最小侵蚀。

6. 发明授权

US06350694B1 Reducing CMP scratch, dishing and erosion by post CMP etch back method for low-k materials 有权
标题翻译：对于低k材料，通过后CMP回蚀法减少CMP划痕，凹陷和侵蚀
公开(公告)号：US06350694B1
公开(公告)日：2002-02-26
申请号：US09814038
申请日：2001-03-22
申请人： Weng Chang , Tien-I Bao , Syun-Ming Jang
发明人： Weng Chang , Tien-I Bao , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： G11C11/406 , G11C11/404 , G11C11/40603 , G11C11/4096 , H01L21/02074 , H01L21/31055 , H01L21/31058 , H01L21/3212 , H01L21/76819 , H01L21/7684
摘要： A new plasma etch back is provided that is applied to the surface of a low-k dielectric after the process of CMP of a copper surface has been completed. The copper surface is the surface of interconnect metal, the interconnect metal is embedded in the layer of low-k dielectric.
摘要翻译：提供了一种新的等离子体回蚀，其在铜表面的CMP处理已经完成之后被施加到低k电介质的表面。铜表面是互连金属的表面，互连金属嵌入在低k电介质层中。

7. 发明授权

US08344447B2 Silicon layer for stopping dislocation propagation 有权
标题翻译：用于阻止位错传播的硅层
公开(公告)号：US08344447B2
公开(公告)日：2013-01-01
申请号：US11732889
申请日：2007-04-05
申请人： Hsien-Hsin Lin , Weng Chang , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Ming-Hua Yu
发明人： Hsien-Hsin Lin , Weng Chang , Chien-Chang Su , Kuan-Yu Chen , Hsueh-Chang Sung , Ming-Hua Yu
IPC分类号： H01L29/94
CPC分类号： H01L29/66477 , H01L21/02532 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.
摘要翻译：提供一种复合半导体结构及其形成方法。复合半导体结构包括第一含硅化合物层，其包含选自基本上由锗和碳组成的组的元素; 所述第一含硅化合物层上的硅层，其中所述硅层包含基本上纯的硅; 以及在所述硅层上包含所述元素的第二含硅化合物层。第一和第二含硅化合物层具有比硅层低的硅浓度。复合半导体结构可以形成为金属氧化物半导体（MOS）器件的源极/漏极区域。

8. 发明授权

US08258588B2 Sealing layer of a field effect transistor 有权
标题翻译：场效应晶体管的密封层
公开(公告)号：US08258588B2
公开(公告)日：2012-09-04
申请号：US12757241
申请日：2010-04-09
申请人： Yu Chao Lin , Jr Jung Lin , Yih-Ann Lin , Jih-Jse Lin , Chao-Cheng Chen , Ryan Chia-Jen Chen , Weng Chang
发明人： Yu Chao Lin , Jr Jung Lin , Yih-Ann Lin , Jih-Jse Lin , Chao-Cheng Chen , Ryan Chia-Jen Chen , Weng Chang
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/4983 , H01L29/6656
摘要： An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.
摘要翻译：场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅极电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管在基板表面几乎没有凹陷。

9. 发明申请

US20080308899A1 TRIANGULAR SPACE ELEMENT FOR SEMICONDUCTOR DEVICE 有权
标题翻译：用于半导体器件的三角形空间元件
公开(公告)号：US20080308899A1
公开(公告)日：2008-12-18
申请号：US11763566
申请日：2007-06-15
申请人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
发明人： Yu-Lien Huang , Yi-Chen Huang , Jim Cy Huang , Weng Chang , Hun-Jan Tao
IPC分类号： H01L29/06 , H01L29/00
CPC分类号： H01L21/823425 , H01L21/823468 , Y10S438/981
摘要： Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.
摘要翻译：提供了包括基板的半导体器件。形成在基板上的栅极。门包括侧壁。在衬底上形成并且邻近门的侧壁的间隔物。间隔件具有基本上三角形的几何形状。在第一栅极和第一间隔物上形成接触蚀刻停止层（CESL）。 CESL的厚度与第一间隔件的宽度在大约0.625和16之间。

10. 发明申请

US20080242108A1 Method for fabricating semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080242108A1
公开(公告)日：2008-10-02
申请号：US11730551
申请日：2007-04-02
申请人： Weng Chang , Fong-Yu Yen , Hun-Jan Tao , Mong-Song Liang
发明人： Weng Chang , Fong-Yu Yen , Hun-Jan Tao , Mong-Song Liang
IPC分类号： H01L21/46
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/67207
摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括提供第一室和第二室。第一室和第二室通过压力差单元连接，用于在第一室中的基板上沉积金属膜，经由压差单元将衬底转移到第二室，而不将衬底暴露于周围环境;以及在第二室中的金属膜上沉积含硅膜。

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