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1. 发明授权

US08835753B2 Solar cell and method of fabricating the same 有权
标题翻译：太阳能电池及其制造方法
公开(公告)号：US08835753B2
公开(公告)日：2014-09-16
申请号：US13101996
申请日：2011-05-05
申请人： Yen-Cheng Hu , Hsin-Feng Li , Zhen-Cheng Wu
发明人： Yen-Cheng Hu , Hsin-Feng Li , Zhen-Cheng Wu
IPC分类号： H01L31/036 , H01L31/0392 , H01L31/18 , H01L31/0747 , H01L31/0368 , H01L31/068
CPC分类号： H01L31/03685 , H01L31/068 , H01L31/0747 , H01L31/1824 , H01L31/1872 , Y02E10/545 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： A solar cell includes a semiconductor base, a first doped semiconductor layer, an insulating layer, a second doped semiconductor layer and a first electrode layer. The semiconductor base has a first doped type. The first doped semiconductor layer, disposed on the semiconductor base, has a doped contact region. The insulating layer is disposed on the first doped semiconductor layer, exposing the doped contact region. The second doped semiconductor layer is disposed on the insulating layer and the doped contact region. The first doped semiconductor layer, the doped contact region and the second doped semiconductor layer have a second doped type, and a dopant concentration of the second doped semiconductor layer is between that of the first doped semiconductor layer and that of the doped contact region. The first electrode layer is disposed corresponding to the doped contact region.
摘要翻译：太阳能电池包括半导体基底，第一掺杂半导体层，绝缘层，第二掺杂半导体层和第一电极层。半导体基底具有第一掺杂型。设置在半导体基底上的第一掺杂半导体层具有掺杂的接触区域。绝缘层设置在第一掺杂半导体层上，暴露掺杂的接触区域。第二掺杂半导体层设置在绝缘层和掺杂接触区域上。第一掺杂半导体层，掺杂接触区域和第二掺杂半导体层具有第二掺杂类型，并且第二掺杂半导体层的掺杂剂浓度在第一掺杂半导体层和掺杂接触区域的掺杂浓度之间。第一电极层对应于掺杂的接触区域设置。

2. 发明申请

US20120171805A1 METHOD OF FABRICATING A SOLAR CELL 有权
标题翻译：制造太阳能电池的方法
公开(公告)号：US20120171805A1
公开(公告)日：2012-07-05
申请号：US13049886
申请日：2011-03-16
申请人： Yen-Cheng Hu , Cheng-Chang Kuo , Jun-Wei Chen , Hsin-Feng Li , Jen-Chieh Chen , Zhen-Cheng Wu
发明人： Yen-Cheng Hu , Cheng-Chang Kuo , Jun-Wei Chen , Hsin-Feng Li , Jen-Chieh Chen , Zhen-Cheng Wu
IPC分类号： H01L31/18
CPC分类号： H01L31/068 , H01L31/186 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a solar cell is provided. A first type semiconductor substrate having a first surface and a second surface is provided. A second type doped diffusion region is formed in parts of the first type semiconductor substrate. The second type doped diffusion region extends within the first type semiconductor substrate from the first surface. An anti-reflection coating (ARC) in contact with second type doped diffusion region is formed over the first surface. A conductive paste including conductive particles and dopant is formed over the ARC. A co-firing process for enabling the conductive paste to penetrate the ARC to form a first contact conductor embedded in the ARC is performed. During the co-firing process, the dopant diffuses into the second type doped diffusion region and a second type heavily doped diffusion region is formed. A second contact conductor is formed on the second surface.
摘要翻译：提供一种制造太阳能电池的方法。提供具有第一表面和第二表面的第一类型的半导体衬底。在第一类型半导体衬底的部分中形成第二类型的掺杂扩散区。第二类掺杂扩散区从第一表面在第一类型半导体衬底内延伸。在第一表面上形成与第二类掺杂扩散区接触的抗反射涂层（ARC）。在ARC上形成包括导电颗粒和掺杂剂的导电浆料。执行用于使导电浆料穿透ARC以形成嵌入ARC中的第一接触导体的共烧制方法。在共烧制过程中，掺杂剂扩散到第二类掺杂扩散区，形成第二类重掺杂扩散区。第二接触导体形成在第二表面上。

3. 发明申请

US20120097236A1 SOLAR CELL 有权
标题翻译：太阳能电池
公开(公告)号：US20120097236A1
公开(公告)日：2012-04-26
申请号：US13100310
申请日：2011-05-04
申请人： Yen-Cheng Hu , Peng Chen , Tsung-Pao Chen , Shuo-Wei Liang , Zhen-Cheng Wu , Chien-Jen Chen
发明人： Yen-Cheng Hu , Peng Chen , Tsung-Pao Chen , Shuo-Wei Liang , Zhen-Cheng Wu , Chien-Jen Chen
IPC分类号： H01L31/0216
CPC分类号： H01L31/0264 , H01L31/02167 , H01L31/02168 , H01L31/18 , Y02E10/50
摘要： A solar cell includes a semi-conductive substrate, a doping layer, an anti-reflection layer, an electrode, a passivation stacked layer and a contact layer. The semi-conductive substrate has a front and a back surface. The doping layer is disposed on the front surface. The anti-reflection layer is disposed on the doping layer. The electrode is disposed on the anti-reflection layer and electrically connected to the doping layer. The passivation stacked layer is disposed on the back surface and has a first dielectric layer, a second dielectric layer and a middle dielectric layer sandwiched between the first and the second dielectric layer. The dielectric constant of the middle dielectric layer is substantially lower than the dielectric constant of the first dielectric layer and the dielectric constant of the second dielectric layer. The contact layer covers the passivation stacked layer and electrically contacts with the back surface of the semi-conductive substrate.
摘要翻译：太阳能电池包括半导体基板，掺杂层，抗反射层，电极，钝化堆叠层和接触层。半导体基板具有前表面和后表面。掺杂层设置在前表面上。抗反射层设置在掺杂层上。电极设置在抗反射层上并与掺杂层电连接。钝化堆叠层设置在背面上，并且具有夹在第一和第二电介质层之间的第一电介质层，第二电介质层和中间电介质层。中间介电层的介电常数基本上低于第一介电层的介电常数和第二介质层的介电常数。接触层覆盖钝化堆叠层并与半导体基板的背面电接触。

4. 发明授权

US07834405B2 Semiconductor device including I/O oxide and nitrided core oxide on substrate 有权
标题翻译：在衬底上包括I / O氧化物和氮化核心氧化物的半导体器件
公开(公告)号：US07834405B2
公开(公告)日：2010-11-16
申请号：US11181915
申请日：2005-07-15
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Pi-Tsung Chen , Ying-Tsung Chen
IPC分类号： H01L29/76
CPC分类号： H01L21/823462 , H01L27/088 , Y10S438/981
摘要： A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the core area, a portion of the core oxide being nitrided, a first polysilicon pattern on the core oxide, an I/O oxide including pure oxide on the semiconductor substrate in the peripheral area, and a second polysilicon pattern on the I/O oxide.
摘要翻译：半导体器件包括半导体衬底，其中半导体衬底包括用于核心电路的核心区域和用于外围电路的外围区域。半导体器件在核心区域中的半导体衬底上具有核心氧化物，核心氧化物的一部分被氮化，核心氧化物上的第一多晶硅图案，在周边区域中的半导体衬底上的纯氧化物的I / O氧化物，以及I / O氧化物上的第二多晶硅图案。

5. 发明申请

US20100213518A1 Impurity Doped UV Protection Layer 审中-公开
标题翻译：杂质掺杂紫外线防护层
公开(公告)号：US20100213518A1
公开(公告)日：2010-08-26
申请号：US12774569
申请日：2010-05-05
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Chung-Chi Ko
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Chung-Chi Ko
IPC分类号： H01L21/31 , H01L29/78
CPC分类号： H01L23/552 , B01D53/9468 , B01D53/9472 , B01D2255/1021 , B01D2255/9022 , B01D2255/9035 , B01D2255/9155 , B01D2257/404 , B01D2257/502 , B01D2257/702 , B01J23/40 , B01J23/42 , B01J29/061 , B01J29/072 , B01J29/763 , B01J35/0006 , B01J35/04 , B01J37/024 , B01J37/0244 , B01J37/0246 , H01L2924/0002 , H01L2924/00
摘要： An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.
摘要翻译：在沉积紫外线固化介电层之前，在半导体工件上形成紫外（UV）保护层。紫外线防护层防止紫外线到达并损坏下层材料层和电气设备。 UV保护层包括掺杂有杂质的硅层，其中杂质包括O，C，H，N或其组合。作为实例，UV保护层可以包括SiOC：H，SiON，SiN，SiCO：H，它们的组合或多层。

6. 发明授权

US07732923B2 Impurity doped UV protection layer 失效
标题翻译：杂质掺杂紫外线保护层
公开(公告)号：US07732923B2
公开(公告)日：2010-06-08
申请号：US11039161
申请日：2005-01-20
申请人： Zhen-Cheng Wu , Yung-Cheng Lu , Chung-Chi Ko
发明人： Zhen-Cheng Wu , Yung-Cheng Lu , Chung-Chi Ko
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , B01D53/9468 , B01D53/9472 , B01D2255/1021 , B01D2255/9022 , B01D2255/9035 , B01D2255/9155 , B01D2257/404 , B01D2257/502 , B01D2257/702 , B01J23/40 , B01J23/42 , B01J29/061 , B01J29/072 , B01J29/763 , B01J35/0006 , B01J35/04 , B01J37/024 , B01J37/0244 , B01J37/0246 , H01L2924/0002 , H01L2924/00
摘要： An ultra-violet (UV) protection layer is formed over a semiconductor workpiece before depositing a UV curable dielectric layer. The UV protection layer prevents UV light from reaching and damaging underlying material layers and electrical devices. The UV protection layer comprises a layer of silicon doped with an impurity, wherein the impurity comprises O, C, H, N, or combinations thereof. The UV protection layer may comprise SiOC:H, SiON, SiN, SiCO:H, combinations thereof, or multiple layers thereof, as examples.
摘要翻译：在沉积紫外线固化介电层之前，在半导体工件上形成紫外（UV）保护层。紫外线防护层防止紫外线到达并损坏下层材料层和电气设备。 UV保护层包括掺杂有杂质的硅层，其中杂质包括O，C，H，N或其组合。作为实例，UV保护层可以包括SiOC：H，SiON，SiN，SiCO：H，它们的组合或多层。

7. 发明授权

US07465676B2 Method for forming dielectric film to improve adhesion of low-k film 有权
标题翻译：用于形成介电膜以改善低k膜的粘附性的方法
公开(公告)号：US07465676B2
公开(公告)日：2008-12-16
申请号：US11409658
申请日：2006-04-24
申请人： Fang Wen Tsai , I-I Chen , Zhen-Cheng Wu , Chih-Lung Lin , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
发明人： Fang Wen Tsai , I-I Chen , Zhen-Cheng Wu , Chih-Lung Lin , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76832 , H01L21/76843
摘要： A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.
摘要翻译：提供了具有改善的低k电介质层和下层之间的粘附性的半导体结构及其形成方法。所述半导体衬底包括半导体衬底上的电介质层，所述电介质层上的粘合层，其中所述粘合层包含初始子层上的过渡子层，并且其中所述过渡子层具有逐渐从下部到上部。在粘合层上形成低k电介质层。在低k电介质层中形成镶嵌开口。过渡子层的顶部具有与低k电介质层的组成基本相似的组成。过渡子层的底部具有与初始子层的组成基本相似的组成。

8. 发明申请

US20080188074A1 Peeling-free porous capping material 审中-公开
标题翻译：无剥离多孔封盖材料
公开(公告)号：US20080188074A1
公开(公告)日：2008-08-07
申请号：US11728623
申请日：2007-03-27
申请人： I-I Chen , Fang Wen Tsai , Zhen-Cheng Wu , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
发明人： I-I Chen , Fang Wen Tsai , Zhen-Cheng Wu , Tien-I Bao , Shwang-Ming Jeng , Chen-Hua Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76829 , H01L21/76835 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a cap layer for an interconnect structure is provided. The method includes providing a substrate; depositing a low-k dielectric layer comprising a first porogen over the substrate; depositing a low-k cap layer comprising a second porogen on the low-k dielectric layer; and curing the low-k dielectric layer and the low-k cap layer simultaneously to remove the first and the second porogens, so that a first porosity in the low-k dielectric layer and a second porosity in the low-k cap layer are created. The second porosity is preferably less than the first porosity. Preferably, the low-k dielectric layer and the low-k cap layer comprise a common set of precursors and porogens, and are in-situ performed.
摘要翻译：提供一种用于形成互连结构的盖层的方法。该方法包括提供基板; 在衬底上沉积包含第一致孔剂的低k电介质层; 在低k电介质层上沉积包含第二致孔剂的低k覆盖层; 并且同时固化低k电介质层和低k覆盖层以除去第一和第二致孔剂，从而产生低k电介质层中的第一孔隙和低k覆盖层中的第二孔隙率。第二孔隙率优选小于第一孔隙率。优选地，低k电介质层和低k覆盖层包含一组共同的前体和致孔剂，并且原位进行。

9. 发明申请

US20070249164A1 METHOD OF FABRICATING AN INTERCONNECT STRUCTURE 审中-公开
标题翻译：制作互连结构的方法
公开(公告)号：US20070249164A1
公开(公告)日：2007-10-25
申请号：US11379384
申请日：2006-04-20
申请人： Pi-Tsung Chen , Zhen-Cheng Wu , Ying-Tsung Chen , Yung-Cheng Lu
发明人： Pi-Tsung Chen , Zhen-Cheng Wu , Ying-Tsung Chen , Yung-Cheng Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76825 , H01L21/76813 , H01L21/76829
摘要： An interconnect structure for a semiconductor device is provided. The interconnect structure for a semiconductor device comprises a substrate having a conductive region thereon, a first dielectric layer having a modified surface portion serving as an etch stop layer and a second dielectric layer having a hardness less than that of the modified surface portion. The interconnect structure for a semiconductor device further comprises a trench-shaped conductive line disposed within the second dielectric layer and a conductive plug disposed within the first dielectric layer and interposed between the trench-shaped conductive line and the conductive region.
摘要翻译：提供了一种用于半导体器件的互连结构。半导体器件的互连结构包括其上具有导电区域的衬底，具有用作蚀刻停止层的改性表面部分的第一介电层和硬度小于改性表面部分的硬度的第二电介质层。用于半导体器件的互连结构还包括设置在第二介电层内的沟槽状导电线和设置在第一电介质层内的介于沟槽状导电线与导电区之间的导电插塞。

10. 发明授权

US07259090B2 Copper damascene integration scheme for improved barrier layers 有权
标题翻译：铜镶嵌一体化方案，用于改进阻挡层
公开(公告)号：US07259090B2
公开(公告)日：2007-08-21
申请号：US10834783
申请日：2004-04-28
申请人： Zhen-Cheng Wu , Yung-Cheng Lu
发明人： Zhen-Cheng Wu , Yung-Cheng Lu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76829 , H01L21/76831
摘要： A metal filled dual damascene structure with a reduced capacitance contribution and method for forming the same, the method including forming a first metal filled damascene lined with a first metal barrier layer thickness in a first dielectric insulating layer; and, forming a second metal filled damascene lined with a second metal barrier layer thickness overlying the first metal filled damascene in a second dielectric insulating layer.
摘要翻译：一种具有降低的电容贡献的金属填充双镶嵌结构及其形成方法，所述方法包括在第一介电绝缘层中形成衬有第一金属阻挡层厚度的第一金属填充镶嵌层; 以及在第二介电绝缘层中形成衬有第二金属阻挡层厚度的第二金属填充镶嵌层，该第二金属阻挡层厚度覆盖第一金属填充镶嵌层。

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