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1. 发明授权

US06383935B1 Method of reducing dishing and erosion using a sacrificial layer 有权
标题翻译：使用牺牲层减少凹陷和侵蚀的方法
公开(公告)号：US06383935B1
公开(公告)日：2002-05-07
申请号：US09687162
申请日：2000-10-16
申请人： Cheng Chung Lin , Chen Hua Yu , Tsu Shih , Weng Chang
发明人： Cheng Chung Lin , Chen Hua Yu , Tsu Shih , Weng Chang
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.
摘要翻译：已知化学机械抛光（CMP）在平坦化表面包括部分填充有金属的宽沟槽时引起凹陷。首先用在CMP下的抛光速率与沟槽中的金属相似的材料填充沟槽已经克服了这个问题。旋转涂层用于此，使得只有沟槽被填充。在CMP之后，除去该材料的任何残余物，留下已经被平坦化到预期程度的表面，而不引入显着的凹陷并且金属的最小侵蚀。

2. 发明授权

US06645864B1 Physical vapor deposition of an amorphous silicon liner to eliminate resist poisoning 有权
标题翻译：非晶硅衬垫的物理气相沉积以消除抗蚀剂中毒
公开(公告)号：US06645864B1
公开(公告)日：2003-11-11
申请号：US10068045
申请日：2002-02-05
申请人： Cheng Chung Lin , Lain Jong Li
发明人： Cheng Chung Lin , Lain Jong Li
IPC分类号： H01L2100
CPC分类号： H01L21/76846 , H01L21/76808 , H01L21/76855
摘要： A layer of low k dielectric is formed on a substrate having a conducting electrode formed therein. A via hole is formed in the low k dielectric exposing the conducting electrode. A thin layer of amorphous silicon is deposited on the layer of low k dielectric and on the sidewalls and bottom of a via hole. A layer of resist is then formed and patterned with a trench pattern. A trench is etched in the layer of low k dielectric directly over the via hole using the patterned layer of resist. The patterned layer of resist is then stripped and the trench and via hole are filled with conducting material. The layer of amorphous silicon prevents amine radicals, NHx, which can be released from the low k dielectric, especially during the via hole etching, from interacting with the resist and forming resist scum resulting in via poisoning.
摘要翻译：在其上形成有导电电极的基板上形成低k电介质层。在暴露导电电极的低k电介质中形成通孔。非晶硅薄层沉积在低k电介质层和通孔的侧壁和底部上。然后形成抗蚀剂层并用沟槽图案构图。使用图案化的抗蚀剂层，在通孔上直接在低k电介质层中蚀刻沟槽。然后剥离图案化的抗蚀剂层，并且用导电材料填充沟槽和通孔。非晶硅层防止胺自由基NH x，其可以从低k电介质释放，特别是在通孔蚀刻期间，与抗蚀剂相互作用并形成导致通过中毒的抗蚀剂浮渣。

3. 发明授权

US06372661B1 Method to improve the crack resistance of CVD low-k dielectric constant material 有权
标题翻译：提高CVD低介电常数材料抗裂性的方法
公开(公告)号：US06372661B1
公开(公告)日：2002-04-16
申请号：US09617011
申请日：2000-07-14
申请人： Cheng Chung Lin , Shwang Ming Jeng , Lain Jong Li
发明人： Cheng Chung Lin , Shwang Ming Jeng , Lain Jong Li
IPC分类号： H01L2131
CPC分类号： H01L21/02126 , C23C16/30 , H01L21/02211 , H01L21/02274 , H01L21/3144 , H01L21/3145 , H01L21/31633 , H01L21/76807 , H01L24/05 , H01L2924/14 , Y10S438/954 , H01L2924/00
摘要： A method of fabricating a CVD low-k SiOCN material. The first embodiment comprising the following steps. MeSiH3, N2O, and N2 are reacted at a molar ratio of from about 1:5:10 to 1:10:15, at a plasma power from about 0 to 400 W to deposit a final deposited film. The final deposited film is treated to stabilize the final deposited film to form a CVD low-k SiOCN material. The second embodiment comprising the following steps. A starting mixture of MeSiH3, SiH4, N2O, and N2 is reacted at a molar ratio of from about 1:1:5:10 to 1:5:10:15, in a plasma in a helium carrier gas at a plasma power from about 0 to 400 W to deposit a CVD low-k SiOCN material.
摘要翻译：一种制造CVD低k SiOCN材料的方法。第一实施例包括以下步骤。 MeSiH 3，N 2 O和N 2以约1:5:10至1:10:15的摩尔比以约0-400W的等离子体功率反应，沉积最后的沉积膜。处理最终沉积的膜以稳定最终沉积膜以形成CVD低k SiOCN材料。第二实施例包括以下步骤。在氦载气中的等离子体中以等离子体功率的等离子体功率，以约1:1:5:10至1:5:10:15的摩尔比使MeSiH 3，SiH 4，N 2 O和N 2的起始混合物反应约0至400W以沉积CVD低k SiOCN材料。

4. 发明授权

US06794295B1 Method to improve stability and reliability of CVD low K dielectric 失效
标题翻译：提高CVD低K电介质稳定性和可靠性的方法
公开(公告)号：US06794295B1
公开(公告)日：2004-09-21
申请号：US09579542
申请日：2000-05-26
申请人： Cheng Chung Lin , Lain-Jong Li
发明人： Cheng Chung Lin , Lain-Jong Li
IPC分类号： H01L21302
CPC分类号： H01L21/02211 , H01L21/022 , H01L21/02274 , H01L21/31604 , H01L21/31608 , H01L21/31629 , H01L21/31633 , H01L21/76807
摘要： A process for depositing, through plasma enhanced chemical vapor deposition, inorganic films having low dielectric constant is disclosed. After deposition under low power for a few seconds the power is raised to high for a few seconds, deposition of the film continuing to alternate between low and high power modes until the total desired thickness is reached. Additionally, for the deposition of materials such as black diamond, oxygen is added to the plasma during the high power phase (and removed during the low power phase). We have found that films deposited in this way have low flat band voltages, close to zero, and are, in general, more robust than films deposited according to prior art methods. In particular, these films are free of the cracking problems often encountered during chemical mechanical polishing of films of this type during the formation of damascene structures.
摘要翻译：公开了通过等离子体增强化学气相沉积沉积具有低介电常数的无机膜的方法。在低功率下沉积几秒钟之后，功率升高到几秒钟，膜的沉积继续在低功率模式和高功率模式之间交替，直到达到总的期望厚度。另外，对于诸如黑色金刚石的材料的沉积，在高功率阶段期间将氧气加入到等离子体中（并且在低功率阶段期间被除去）。我们已经发现以这种方式沉积的薄膜具有接近于零的低平带电压，并且通常比根据现有技术方法沉积的薄膜更坚固。特别地，这些膜在形成镶嵌结构期间没有这种类型的膜的化学机械抛光期间经常遇到的龟裂问题。

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