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1. 发明申请

US20050236694A1 Silicon oxycarbide and silicon carbonitride based materials for MOS devices 有权
标题翻译：用于MOS器件的碳氧化硅和碳氮化硅基材料
公开(公告)号：US20050236694A1
公开(公告)日：2005-10-27
申请号：US10895514
申请日：2004-07-21
申请人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
发明人： Zhen-Cheng Wu , H. Tsai , Da-Wen Lin , Weng Chang , Shwang-Ming Cheng , Mong Liang
IPC分类号： H01L21/31 , H01L21/314 , H01L21/316 , H01L21/336 , H01L21/768 , H01L23/31 , H01L23/58 , H01L29/49
CPC分类号： H01L29/4983 , H01L21/02126 , H01L21/02167 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/314 , H01L21/3148 , H01L21/31633 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/3192 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： In the preferred embodiment, a gate dielectric and an electrode are formed on a substrate. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. Spacers are preferably formed of SiCO based material or SiCN based material. The source and drain are then formed. A contact etch stop (CES) layer is formed on the source/drain regions and the spacers. The CES layer is preferably formed of SiCO based material or SiCN based material. An Inter-Level Dielectric (ILD) is then formed on the CES layer.
摘要翻译：在优选实施例中，在基板上形成栅极电介质和电极。在栅电极和栅极电介质的相对侧壁上形成一对间隔物。间隔物优选由SiCO基材料或SiCN基材料形成。然后形成源极和漏极。在源极/漏极区域和间隔物上形成接触蚀刻停止层（CES）层。 CES层优选由SiCO基材料或SiCN基材料形成。然后在CES层上形成级间介质（ILD）。

2. 发明授权

US06900269B2 Halogen-free resin composition 有权
标题翻译：无卤树脂组合物
公开(公告)号：US06900269B2
公开(公告)日：2005-05-31
申请号：US10412126
申请日：2003-04-11
申请人： Kuen-Yuan Hwang , An-Pang Tu , Mong Liang , Chi-Yi Ju , Sheng-Yen Wu , Chun-Hsiung Kao , Fang-Shian Su
发明人： Kuen-Yuan Hwang , An-Pang Tu , Mong Liang , Chi-Yi Ju , Sheng-Yen Wu , Chun-Hsiung Kao , Fang-Shian Su
IPC分类号： C09K21/14 , C08G59/30 , C08G59/40 , C08G59/50 , C08K3/00 , C08L63/00 , C08L63/02 , C08L71/12 , C09D11/00 , C09J7/00 , C09J163/00 , C09J171/10 , H05K1/03
CPC分类号： C08G59/5046 , C08G59/304 , C08L63/00 , C08L71/12 , H05K1/0326 , C08L2666/22
摘要： Disclosed is a halogen-free resin composition comprising: (A) one or more phosphorus-containing epoxy resins; (B) a hardener; (C) a hardening accelerator; (D) a polyphenylene oxide resin; and (E) a filling material, wherein the hardener of component B has the structure represented by the following formula (I): wherein each symbol is as defined above. The halogen-free resin composition of the present invention without adding halogen has excellent heat resistance and flame retardant property, and excellent dielectric property. The halogen-free resin composition of the present invention is particularly useful in the application of bonding sheets, composite materials, laminated plates, printed circuit boards, copper foil adhesives, inks used for build-up process, semiconductor packaging materials and the like.
摘要翻译：公开了一种无卤树脂组合物，其包含：（A）一种或多种含磷环氧树脂; （B）硬化剂; （C）硬化促进剂; （D）聚苯醚树脂; 和（E）填充材料，其中组分B的硬化剂具有由下式（I）表示的结构：其中每个符号如上所定义。不添加卤素的本发明的无卤树脂组合物具有优异的耐热性和阻燃性，并且具有优异的介电性能。本发明的无卤素树脂组合物特别适用于粘合片，复合材料，层压板，印刷电路板，铜箔粘合剂，用于堆积工艺的油墨，半导体包装材料等的应用。

3. 发明授权

US5241017A Thionyl phosphazene polymers 失效
标题翻译：三聚磷酸酯聚合物
公开(公告)号：US5241017A
公开(公告)日：1993-08-31
申请号：US848940
申请日：1992-03-10
申请人： Ian Manners , Mong Liang , Andreas Ostrowicki
发明人： Ian Manners , Mong Liang , Andreas Ostrowicki
IPC分类号： C08G79/02 , C08G79/00 , C08J3/24 , C08L85/02
CPC分类号： C08G79/00
摘要： The new thionyl phosphazene polymers, which contain recurring structural units corresponding to the following formula ##STR1## are prepared by ring-opening polymerization of cyclothionyl chlorophosphazene corresponding to the following formula ##STR2## at temperatures of 100.degree. to 300.degree. C. in the presence of an inert organic solvent and reaction of the polymer thus obtained, which corresponds to the following formula ##STR3## with salts corresponding to the following formulaM(R.sup.1 -R.sup.5)in the presence of an inert organic solvent at temperatures of 20.degree. to 200.degree. C.The new thionyl phosphazene polymers may be used for the production of thermoplastics, elastomers or thermosets.
摘要翻译：含有对应于下式“IMAGE”的重复结构单元的新的亚硫酰基磷腈聚合物是通过在100℃至300℃的温度下在相应于下式“IMAGE”的环硫酰氯基膦腈的开环聚合制备的的惰性有机溶剂，并且在惰性有机溶剂存在下，在20℃至200℃的温度下，将由此得到的聚合物与下式（IMAGE）与对应于下式M（R 1 -R 5）的盐反应新的亚硫酰基磷腈聚合物可用于生产热塑性塑料，弹性体或热固性材料。

4. 发明申请

US20070010073A1 Method of forming a MOS device having a strained channel region 审中-公开
标题翻译：形成具有应变通道区域的MOS器件的方法
公开(公告)号：US20070010073A1
公开(公告)日：2007-01-11
申请号：US11175563
申请日：2005-07-06
申请人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
发明人： Chien-Hao Chen , Chun-Feng Nieh , Tze-Liang Lee , Shih-Chang Chen , Mong Liang
IPC分类号： H01L21/20 , H01L21/4763
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/76828 , H01L21/76829 , H01L21/823412 , H01L21/82345 , H01L21/823807 , H01L21/823842 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device comprising providing a substrate comprising a first device region, implanting a source/drain region in the first device region, forming a strained capping layer on the source/drain region, super annealing and crystallizing the source/drain region, and removing substantially all of the strained capping layer is provided. The method further includes pre-amorphizing the source/drain region before the super annealing. The strained capping layer may further be formed on a pre-amorphized gate electrode, and the gate electrode is super annealed. The strain is generated and preserved after the removal of the strained capping layer.
摘要翻译：一种形成半导体器件的方法，包括提供包括第一器件区域的衬底，在第一器件区域中注入源极/漏极区域，在源极/漏极区域上形成应变封盖层，超退火并使源极/漏极区域结晶并且提供基本上所有的应变封盖层的去除。该方法还包括在超退火之前对源极/漏极区进行非晶化。应变封盖层可以进一步形成在非晶化的栅电极上，并且栅电极被超退火。在去除应变封盖层后产生并保存菌株。

5. 发明申请

US20070013070A1 Semiconductor devices and methods of manufacture thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070013070A1
公开(公告)日：2007-01-18
申请号：US11159709
申请日：2005-06-23
申请人： Mong Liang , Hun-Jan Tao , Jim Huang , Ling-Yen Yeh , Yu-Lien Huang
发明人： Mong Liang , Hun-Jan Tao , Jim Huang , Ling-Yen Yeh , Yu-Lien Huang
IPC分类号： H01L23/52
CPC分类号： H01L21/02123 , H01L21/3185 , H01L27/10894 , H01L27/11
摘要： Novel etch stop layers for semiconductor devices and methods of forming thereof are disclosed. In one embodiment, an etch stop layer comprises tensile or compressive stress. In another embodiments, etch stop layers are formed having a first thickness in a first region of a workpiece and at least one second thickness in a second region of a workpiece, wherein the at least one second thickness is different than the first thickness. The etch stop layer may be thicker over top surfaces than over sidewall surfaces. The etch stop layer may be thicker over widely-spaced feature regions and thinner over closely-spaced feature regions.
摘要翻译：公开了用于半导体器件的新型蚀刻停止层及其形成方法。在一个实施例中，蚀刻停止层包括拉伸或压缩应力。在另一个实施例中，在工件的第一区域中形成具有第一厚度并且在工件的第二区域中具有至少一个第二厚度的蚀刻停止层，其中至少一个第二厚度不同于第一厚度。蚀刻停止层可以在顶表面上比在侧壁表面上更厚。蚀刻停止层可以在宽间隔的特征区域上更厚，并且在紧密间隔的特征区域上更薄。

6. 发明申请

US20060286758A1 Super anneal for process induced strain modulation 有权
公开(公告)号：US20060286758A1
公开(公告)日：2006-12-21
申请号：US11199011
申请日：2005-08-08
申请人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
发明人： Mong Liang , Chien-Hao Chen , Chun-Feng Nieh , Pang-Yen Tsai , Tze-Liang Lee , Shih-Chang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/7624 , H01L21/823468 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for forming a semiconductor structure includes providing a substrate, forming a first device region on the substrate, forming a stressor layer overlying the first device region, and super annealing the stressor layer in the first device region, preferably by exposing the substrate to a high-energy radiance source, so that the stressor layer is super annealed for a substantially short duration. Preferably, the method further includes masking a second device region on the substrate while the first device region is super annealed. Alternatively, after the stressor layer in the first region is annealed, the stressor layer in the second device region is super annealed. A semiconductor structure formed using the method has different strains in the first and second device regions.

7. 发明申请

US20060270166A1 Laser spike annealing for gate dielectric materials 审中-公开
标题翻译：栅极电介质材料的激光尖峰退火
公开(公告)号：US20060270166A1
公开(公告)日：2006-11-30
申请号：US11140766
申请日：2005-05-31
申请人： Liang-Gi Yao , Ming-Ho Yang , Shih-Chang Chen , Mong Liang
发明人： Liang-Gi Yao , Ming-Ho Yang , Shih-Chang Chen , Mong Liang
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/268 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659
摘要： A method of forming a semiconductor device using laser spike annealing is provided. The method includes providing a semiconductor substrate having a surface, forming a gate dielectric layer on the surface of the semiconductor substrate, laser spike annealing the gate dielectric layer, and patterning the gate dielectric layer and thus forming at least a gate dielectric. Source and drain regions are then formed to form a transistor. A capacitor is formed by connecting the source and drain regions.
摘要翻译：提供了使用激光尖峰退火形成半导体器件的方法。该方法包括提供具有表面的半导体衬底，在半导体衬底的表面上形成栅极电介质层，对栅介质层进行激光尖峰退火，以及图案化栅介质层，从而形成至少栅极电介质。然后形成源区和漏区以形成晶体管。通过连接源极和漏极区域形成电容器。

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