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1. 发明授权

US5670389A Semiconductor-on-insulator device having a laterally-graded channel region and method of making 失效
标题翻译：具有横向梯度通道区域的绝缘体上半导体器件及其制造方法
公开(公告)号：US5670389A
公开(公告)日：1997-09-23
申请号：US585137
申请日：1996-01-11
申请人： Wen-Ling Margaret Huang , Hyungcheol Shin , Marco Racanelli
发明人： Wen-Ling Margaret Huang , Hyungcheol Shin , Marco Racanelli
IPC分类号： H01L21/336 , H01L29/786 , H01L21/265 , H01L21/84
CPC分类号： H01L29/78696 , H01L29/66772 , H01L29/78621
摘要： A silicon-on-insulator semiconductor device (40) having laterally-graded channel regions (23A, 24A) and a method of making the silicon-on-insulator semiconductor device (40). The silicon-on-insulator semiconductor device (40) has a gate structure (16) having sidewalls (19, 21) on a semiconductor layer (12). Lightly doped regions (26A, 27A) extend through an entire thickness of a portion of the semiconductor layer (12) under the sidewalls (19, 21). A laterally-graded channel region (23A) is formed below the gate structure (16) and abutting one (26A) of the lightly doped regions. A source (33) is formed in a first (26A) of the lightly doped regions and a drain region (34) is formed in a second (27A) of the lightly doped regions.
摘要翻译：具有横向梯度沟道区（23A，24A）的绝缘体上半导体器件（40）以及制造绝缘体上硅半导体器件（40）的方法。绝缘体上硅半导体器件（40）具有在半导体层（12）上具有侧壁（19,21）的栅极结构（16）。轻掺杂区域（26A，27A）在侧壁（19,21）下延伸穿过半导体层（12）的一部分的整个厚度。在栅极结构（16）的下方形成横向梯度的沟道区（23A），并邻接一个（26A）的轻掺杂区。源极（33）形成在轻掺杂区域的第一（26A）中，并且在第二（27A）轻掺杂区域中形成漏极区域（34）。

2. 发明授权

US5780352A Method of forming an isolation oxide for silicon-on-insulator technology 失效
标题翻译：形成绝缘体上硅技术的隔离氧化物的方法
公开(公告)号：US5780352A
公开(公告)日：1998-07-14
申请号：US553801
申请日：1995-10-23
申请人： Heemyong Park , Wen-Ling Margaret Huang , Juergen Foerstner , Marco Racanelli
发明人： Heemyong Park , Wen-Ling Margaret Huang , Juergen Foerstner , Marco Racanelli
IPC分类号： H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762 , H01L27/12
CPC分类号： H01L21/76264 , H01L21/32 , H01L21/76281
摘要： A method of forming an isolation oxide (30) on a silicon-on-insulator (SOI) substrate (21) includes disposing a mask layer (26, 27) over a region of a silicon layer (24) of the SOI substrate (21). The isolation oxide (30) is grown in a different region (28) of the silicon layer (24). The isolation oxide (30) is grown to a depth (32) within the silicon layer (24) of less than or equal to a thickness (29) of the silicon layer (24). After removing the mask layer (26, 27), the isolation oxide (30) is further grown in the different region (28) of the silicon layer (24) such that the isolation oxide (30) is coupled to a buried electrically insulating layer (23) within the SOI substrate (21). The buried electrically insulating layer (23) and the isolation oxide (30) electrically isolate an active region (43) of a semiconductor device (20).
摘要翻译：在绝缘体上硅（SOI）衬底（21）上形成隔离氧化物（30）的方法包括在SOI衬底（21）的硅层（24）的区域上设置掩模层（26,27））。隔离氧化物（30）生长在硅层（24）的不同区域（28）中。隔离氧化物（30）生长到硅层（24）内的深度（32）小于或等于硅层（24）的厚度（29）。在去除掩模层（26,27）之后，隔离氧化物（30）进一步生长在硅层（24）的不同区域（28）中，使得隔离氧化物（30）与掩埋电绝缘层（23）内。埋入的电绝缘层（23）和隔离氧化物（30）电绝缘半导体器件（20）的有源区（43）。

3. 发明授权

US06627511B1 Reduced stress isolation for SOI devices and a method for fabricating 失效
标题翻译：降低SOI器件的应力隔离和制造方法
公开(公告)号：US06627511B1
公开(公告)日：2003-09-30
申请号：US08508874
申请日：1995-07-28
申请人： Marco Racanelli , Hyungcheol Shin , Heemyong Park
发明人： Marco Racanelli , Hyungcheol Shin , Heemyong Park
IPC分类号： H01L2176
CPC分类号： H01L21/76264 , H01L21/32 , H01L21/76267 , H01L21/76275 , H01L21/76281
摘要： A method for forming an isolation structure (22) on a SOI substrate (11) is provided. A three layer stack of an etchant barrier layer (16), a stress relief layer (17), and an oxide mask layer (18) is formed on the SOI substrate (11). The three layer stack is patterned and etched to expose portions of the etchant barrier layer (16). The silicon layer (13) below the exposed portions of the etchant barrier layer (16) is oxidized to form the isolation structure (22). The isolation structure (22) comprises a bird's head region (21) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure (22) that leaves the SOI substrate (11) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.
摘要翻译：提供了一种在SOI衬底（11）上形成隔离结构（22）的方法。在SOI衬底（11）上形成蚀刻剂阻挡层（16），应力消除层（17）和氧化物掩模层（18）的三层堆叠。图案化和蚀刻三层堆叠以暴露蚀刻剂阻挡层（16）的部分。在蚀刻剂阻挡层（16）的暴露部分下面的硅层（13）被氧化以形成隔离结构（22）。隔离结构（22）包括具有小的侵入的鸟头区域（21），其导致较高的边缘阈值电压。该方法需要最小的过氧化并提供使SOI衬底（11）平坦离开的隔离结构（22）。最小的过氧化减少了在氧化过程中形成的位错数，并且改善了器件的源漏漏。

4. 发明授权

US07078310B1 Method for fabricating a high density composite MIM capacitor with flexible routing in semiconductor dies 有权
标题翻译：在半导体管芯中制造具有柔性布线的高密度复合MIM电容器的方法
公开(公告)号：US07078310B1
公开(公告)日：2006-07-18
申请号：US10850187
申请日：2004-05-19
申请人： Arjun Kar-Roy , Marco Racanelli , Paul Kempf
发明人： Arjun Kar-Roy , Marco Racanelli , Paul Kempf
IPC分类号： H01L21/20
CPC分类号： H01L28/60 , H01L21/76838 , H01L23/5223 , H01L27/0805 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a structure comprises an electrode of a lower MIM capacitor situated in a first interconnect metal layer of a semiconductor die. The structure further comprises a shared electrode of the lower MIM capacitor and an upper MIM capacitor. The structure further comprises an electrode of the upper MIM capacitor situated over the shared electrode. The electrode of the upper MIM capacitor is coupled to the electrode of the lower MIM capacitor through vias and a second interconnect metal layer. In one embodiment, the electrode of the upper MIM capacitor can be divided into two or more segments to allow additional paths for connectivity to reduce the resistance of an electrode of the composite MIM capacitor. In other embodiments, a method for fabricating various embodiments of the composite MIM capacitor is disclosed.
摘要翻译：根据一个实施例，结构包括位于半导体管芯的第一互连金属层中的下部MIM电容器的电极。该结构还包括下MIM电容器的共享电极和上MIM电容器。该结构还包括位于共享电极上方的上MIM电容器的电极。上MIM电容器的电极通过通孔和第二互连金属层耦合到下MIM电容器的电极。在一个实施例中，上MIM电容器的电极可以被划分成两个或更多个段，以允许用于连接的附加路径来降低复合MIM电容器的电极的电阻。在其他实施例中，公开了一种用于制造复合MIM电容器的各种实施例的方法。

5. 发明授权

US07064361B1 NPN transistor having reduced extrinsic base resistance and improved manufacturability 有权
标题翻译： NPN晶体管具有降低的外部基极电阻和改进的可制造性
公开(公告)号：US07064361B1
公开(公告)日：2006-06-20
申请号：US10865634
申请日：2004-06-10
申请人： David Howard , Marco Racanelli , Greg D. U'Ren
发明人： David Howard , Marco Racanelli , Greg D. U'Ren
IPC分类号： H01L29/739
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/1004 , H01L29/167 , H01L29/66242 , H01L29/66272
摘要： According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.
摘要翻译：根据一个示例性实施例，NPN双极晶体管包括位于集电极上方的基极层，其中基极层包含本征基极区域和外部基极区域。 NPN双极晶体管可以是例如NPN硅 - 锗异质结双极晶体管。基层可以是例如硅 - 锗。根据该示例性实施例，NPN双极晶体管还包括位于基极层之上的覆盖层，其中覆盖层的一部分位于外部本体区域之上，并且其中覆盖层的位于外部基极区域之上的部分包括铟掺杂剂。盖层可以是例如多晶硅。根据该示例性实施例，NPN双极晶体管还可以包括位于本征基极区域上方的发射极。发射极可以是例如多晶硅。

6. 发明授权

US06759729B1 Temperature insensitive resistor in an IC chip 有权
标题翻译： IC芯片中的温度不敏感电阻
公开(公告)号：US06759729B1
公开(公告)日：2004-07-06
申请号：US10272888
申请日：2002-10-16
申请人： Marco Racanelli , Chun Hu , Bruce Shen
发明人： Marco Racanelli , Chun Hu , Bruce Shen
IPC分类号： H01L2900
CPC分类号： H01L28/24 , H01L27/0802 , H01L28/20
摘要： According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.
摘要翻译：根据一个示例性实施例，集成电路芯片包括氧化物区域。集成电路芯片还包括具有第一端子和第二端子的聚电阻器，其中多晶硅电阻器位于氧化物区域上方。根据该示例性实施例，集成电路芯片还包括具有第一端子和第二端子的金属电阻器，其中金属电阻器位于多晶硅电阻器上方，并且金属电阻器的第一端子连接到第一端子的聚电阻。根据该示例性实施例，集成电路芯片还可以包括连接到金属电阻器的第二端子的第一金属段和连接到多晶硅电阻器的第二端子的第二金属段。集成电路芯片还可以包括位于多个电阻器和金属电阻器之间的层间电介质。

7. 发明授权

US06716711B1 Method for fabricating a self-aligned emitter in a bipolar transistor 有权
标题翻译：在双极晶体管中制造自对准发射极的方法
公开(公告)号：US06716711B1
公开(公告)日：2004-04-06
申请号：US10308661
申请日：2002-12-02
申请人： Marco Racanelli
发明人： Marco Racanelli
IPC分类号： H01L21331
CPC分类号： H01L29/66242
摘要： In one disclosed embodiment, a silicon-germanium base is formed, which includes an extrinsic base region, a link base region, and an intrinsic base region. An etch stop layer, which can be silicon oxide, is deposited over the silicon-germanium base. A polycrystalline silicon layer is then formed on the etch stop layer above the silicon-germanium base. The polycrystalline silicon layer is patterned to form a temporary emitter. The link base regions can be implant doped after fabricating the temporary emitter, for example, to reduce the resistance of the link base regions. Link spacers are then fabricated on the sides of the temporary emitter. The link spacers can be formed by depositing a conformal layer of silicon oxide over the temporary emitter and then etching back the conformal layer. The length of the link base regions, which are below the spacers, can be determined by the deposition thickness of the conformal layer. The extrinsic base regions are implant doped after fabricating the link spacers. A protective layer of silicon oxide can be deposited over the extrinsic base regions, link spacers and temporary emitter prior to patterning the temporary emitter and link spacers by opening a photoresist mask. The temporary emitter is then etched away and the etch stop layer is removed, forming a cavity between the link spacers. A final emitter is then formed in the cavity. For example, the final emitter can be formed by depositing polycrystalline silicon in the cavity and forming a base-emitter junction within the intrinsic base region.
摘要翻译：在一个公开的实施例中，形成硅 - 锗基底，其包括外在基极区域，连接基极区域和本征基极区域。可以在硅 - 锗基底上沉积可以是氧化硅的蚀刻停止层。然后在硅 - 锗基底上的蚀刻停止层上形成多晶硅层。图案化多晶硅层以形成临时发射体。例如，在制造临时发射极之后，链路基极区域可以被注入掺杂，以减小链路基极区域的电阻。然后在临时发射器的侧面上制造连接间隔物。连接间隔物可以通过在临时发射体上沉积氧化硅保形层，然后蚀刻保形层来形成。可以通过保形层的沉积厚度来确定在间隔物之下的连接基区的长度。外部基极区域在制造链路间隔物之后是注入掺杂的。在通过打开光致抗蚀剂掩模来形成临时发射极和连接间隔物之前，可以在外部基极区域，连接间隔物和临时发射体之间沉积氧化硅保护层。然后蚀刻掉临时发射体，去除蚀刻停止层，在连接间隔物之间形成空腔。然后在空腔中形成最终的发射极。例如，最终发射极可以通过在腔内沉积多晶硅并在本征基极区内形成基极 - 发射极结而形成。

8. 发明授权

US06475849B2 Method for reducing base resistance in a bipolar transistor 有权
标题翻译：降低双极型晶体管的基极电阻的方法
公开(公告)号：US06475849B2
公开(公告)日：2002-11-05
申请号：US10133690
申请日：2002-04-26
申请人： Marco Racanelli
发明人： Marco Racanelli
IPC分类号： H01L218238
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance. Moreover, a structure comprising a base region with reduced link base resistance can be fabricated according to the disclosed method.
摘要翻译：根据所公开的方法，在将本征基极区域与外部基极区域连接的链路基区域中形成掺杂尖峰区域。例如，本征基极区域可以是在硅 - 锗异质结双极晶体管中形成基极 - 发射极结的区域，并且外部基极区域可以是与外部电极相同的晶体管的基极的外部部分联系做了。掺杂剂尖峰可以是增加的硼掺杂剂的浓度。然后在链路基区域的顶部上制造扩散阻挡段，以防止掺杂物尖峰从链路基区扩散。例如，扩散阻挡链段可以由氧化硅形成。因此，例如，通过在掺杂剂尖峰区域中较高浓度的硼掺杂剂导致链路基极电阻低于本征基极电阻，降低了基极电阻。此外，可以根据所公开的方法制造包括具有降低的基极电阻的基极区域的结构。

9. 发明授权

US06410975B1 Bipolar transistor with reduced base resistance 有权
标题翻译：具有降低的基极电阻的双极晶体管
公开(公告)号：US06410975B1
公开(公告)日：2002-06-25
申请号：US09653982
申请日：2000-09-01
申请人： Marco Racanelli
发明人： Marco Racanelli
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L29/1004 , H01L29/7378
摘要： According to a disclosed method, a dopant spike region is formed in a link base region, which connects an intrinsic base region to an extrinsic base region. For example, the intrinsic base region can be the region in which the base-emitter junction is formed in a silicon-germanium heterojunction bipolar transistor, and the extrinsic base region can be the external portion of the base of the same transistor to which external electrical contact is made. The dopant spike can be an increased concentration of boron dopant. A diffusion blocking segment is then fabricated on top of the link base region in order to prevent diffusion of the dopant spike out of the link base region. For example, the diffusion blocking segment can be formed from silicon-oxide. Thus, link base resistance is reduced, for example, by the higher concentration of boron dopant in the dopant spike region causing the link base resistance to be lower than the intrinsic base resistance. Moreover, a structure comprising a base region with reduced link base resistance can be fabricated according to the disclosed method.
摘要翻译：根据所公开的方法，在将本征基极区域与外部基极区域连接的链路基区域中形成掺杂尖峰区域。例如，本征基极区域可以是在硅 - 锗异质结双极晶体管中形成基极 - 发射极结的区域，并且外部基极区域可以是与外部电极相同的晶体管的基极的外部部分联系做了。掺杂剂尖峰可以是增加的硼掺杂剂的浓度。然后在链路基区域的顶部上制造扩散阻挡段，以防止掺杂物尖峰从链路基区扩散。例如，扩散阻挡链段可以由氧化硅形成。因此，例如，通过在掺杂剂尖峰区域中较高浓度的硼掺杂剂导致链路基极电阻低于本征基极电阻，降低了基极电阻。此外，可以根据所公开的方法制造包括具有降低的基极电阻的基极区域的结构。

10. 发明授权

US09412758B2 Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication 有权
标题翻译：具有更可预测的结电容的绝缘体半导体（SOI）结构和制造方法
公开(公告)号：US09412758B2
公开(公告)日：2016-08-09
申请号：US12286471
申请日：2008-09-29
申请人： Robert L. Zwingman , Marco Racanelli
发明人： Robert L. Zwingman , Marco Racanelli
IPC分类号： H01L21/70 , H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/76264 , H01L21/84
摘要： A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over the buried oxide layer. At least one transistor is fabricated in the device layer, wherein a source/drain junction of the transistor does not contact the buried oxide layer, thereby causing the source/drain junction to have a source/drain junction capacitance. The SOI structure also comprises at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thereby electrically isolating the at least one transistor. In one embodiment the at least one trench is formed after fabrication of the at least one transistor and is filled with only dielectric. In one embodiment, one or more wells may be formed in the device layer. In one embodiment the bulk semiconductor layer has a high resistivity of typically about 1000 ohms-centimeter or greater.
摘要翻译：所公开的实施例是在体半导体层上包括掩埋氧化物层的绝缘体上半导体（SOI）结构，以及在掩埋氧化物层上的器件层。在器件层中制造至少一个晶体管，其中晶体管的源极/漏极结不与掩埋氧化物层接触，从而使源极/漏极结具有源极/漏极结电容。 SOI结构还包括延伸穿过器件层并且与掩埋氧化物层的顶表面接触的至少一个沟槽，从而电隔离至少一个晶体管。在一个实施例中，在制造至少一个晶体管之后形成至少一个沟槽，并且仅填充电介质。在一个实施例中，可以在器件层中形成一个或多个阱。在一个实施例中，体半导体层具有通常约1000欧姆厘米或更大的高电阻率。

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