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    • 1. 发明授权
    • Temperature insensitive resistor in an IC chip
    • IC芯片中的温度不敏感电阻
    • US06759729B1
    • 2004-07-06
    • US10272888
    • 2002-10-16
    • Marco RacanelliChun HuBruce Shen
    • Marco RacanelliChun HuBruce Shen
    • H01L2900
    • H01L28/24H01L27/0802H01L28/20
    • According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.
    • 根据一个示例性实施例,集成电路芯片包括氧化物区域。 集成电路芯片还包括具有第一端子和第二端子的聚电阻器,其中多晶硅电阻器位于氧化物区域上方。 根据该示例性实施例,集成电路芯片还包括具有第一端子和第二端子的金属电阻器,其中金属电阻器位于多晶硅电阻器上方,并且金属电阻器的第一端子连接到第一端子 的聚电阻。 根据该示例性实施例,集成电路芯片还可以包括连接到金属电阻器的第二端子的第一金属段和连接到多晶硅电阻器的第二端子的第二金属段。 集成电路芯片还可以包括位于多个电阻器和金属电阻器之间的层间电介质。
    • 2. 发明授权
    • Double-implant high performance varactor and method for manufacturing same
    • 双种植体高性能变容二极管及其制造方法
    • US06995068B1
    • 2006-02-07
    • US09590462
    • 2000-06-09
    • Marco RacanelliChun HuPhil N. Sherman
    • Marco RacanelliChun HuPhil N. Sherman
    • H01L21/76
    • H01L29/66174H01L29/93
    • A varactor designed to enable voltage controlled oscillator (VCO) integration in wireless systems is the base-emitter junction of a specially optimized NPN device formed with a double base implant. A first, shallow implant optimizes capacitance, leakage current, and tuning range. A second, deeper base implant is used to improve the quality factor of the device by reducing the base resistance. The varactor includes a third terminal (collector), which isolates the emitter-base junction from the substrate, providing flexibility in circuit applications. A method for fabricating a high performance varactor having the above-described structure is also provided.
    • 设计用于在无线系统中实现压控振荡器(VCO)集成的变容二极管是由双基底植入物形成的特别优化的NPN器件的基极 - 发射极结。 第一个浅的注入优化电容,漏电流和调谐范围。 第二个更深的基底植入物用于通过降低基极电阻来改善器件的品质因数。 变容二极管包括第三端子(集电极),其将发射极 - 基极结与衬底隔离,在电路应用中提供灵活性。 还提供了一种制造具有上述结构的高性能变容二极管的方法。
    • 3. 发明授权
    • Composite series resistor having reduced temperature sensitivity in an IC chip
    • 复合串联电阻在IC芯片中具有降低的温度灵敏度
    • US07078786B1
    • 2006-07-18
    • US10843190
    • 2004-05-10
    • Marco RacanelliChun HuChih-Chieh Shen
    • Marco RacanelliChun HuChih-Chieh Shen
    • H01L29/00
    • H01L28/24H01L27/0802H01L28/20
    • According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. According to this exemplary embodiment, the integrated circuit chip further comprises a metal resistor having a first terminal and a second terminal, where the metal resistor is situated over the poly resistor, and where the first terminal of the metal resistor is connected to the first terminal of the poly resistor. According to this exemplary embodiment, the integrated circuit chip may further comprise a first metal segment connected to the second terminal of the metal resistor and a second metal segment connected to the second terminal of the poly resistor. The integrated circuit chip may further comprise an inter-layer dielectric situated between the poly resistor and the metal resistor.
    • 根据一个示例性实施例,集成电路芯片包括氧化物区域。 集成电路芯片还包括具有第一端子和第二端子的聚电阻器,其中多晶硅电阻器位于氧化物区域上方。 根据该示例性实施例,集成电路芯片还包括具有第一端子和第二端子的金属电阻器,其中金属电阻器位于多晶硅电阻器上方,并且金属电阻器的第一端子连接到第一端子 的聚电阻。 根据该示例性实施例,集成电路芯片还可以包括连接到金属电阻器的第二端子的第一金属段和连接到多晶硅电阻器的第二端子的第二金属段。 集成电路芯片还可以包括位于多个电阻器和金属电阻器之间的层间电介质。