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1. 发明授权

US07811915B2 Method for forming bit lines for semiconductor devices 有权
标题翻译：用于形成半导体器件的位线的方法
公开(公告)号：US07811915B2
公开(公告)日：2010-10-12
申请号：US12048549
申请日：2008-03-14
申请人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
发明人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L21/22
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.
摘要翻译：一种形成半导体器件的方法包括在衬底的第一部分上形成第一介电层，在第一介电层上形成电荷存储层，并蚀刻电荷存储层和第一介电层中的沟槽，其中沟槽延伸到基底。该方法还包括将n型杂质注入到衬底中以形成具有第一深度和第一宽度的n型区域，并且在植入n型杂质之后将p型杂质注入到衬底中，形成p型杂质具有第二深度和第二宽度的p型区域。该方法还包括在电荷存储层上形成第二电介质层，并在第二电介质层上形成控制栅极。

2. 发明授权

US07018868B1 Disposable hard mask for memory bitline scaling 有权
标题翻译：用于存储器位线缩放的一次性硬掩模
公开(公告)号：US07018868B1
公开(公告)日：2006-03-28
申请号：US10770245
申请日：2004-02-02
申请人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
发明人： Jean Y. Yang , Jeff P. Erhardt , Cyrus Tabery , Weidong Qian , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal
IPC分类号： H01L21/44
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： The invention is a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes buried bitlines in a semiconductor substrate. Additionally, doped regions are formed adjacent the buried bitlines. The doped regions adjacent the buried bitlines inhibit a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和半导体器件的制造方法。半导体器件包括在半导体衬底中的掩埋位线。此外，掺杂区域形成在掩埋位线附近。与掩埋位线相邻的掺杂区域可以防止掩埋位线之间的漏电流。

3. 发明授权

US07972948B2 Method for forming bit lines for semiconductor devices 有权
标题翻译：用于形成半导体器件的位线的方法
公开(公告)号：US07972948B2
公开(公告)日：2011-07-05
申请号：US12880541
申请日：2010-09-13
申请人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
发明人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L21/22
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity.
摘要翻译：存储器件包括多个存储器单元和多个位线。每个位线包括具有第一宽度和第一深度的第一区域和具有第二宽度和第二深度的第二区域，其中第一宽度小于第二宽度。第一区域可以包括n型杂质，第二区域可以包括p型杂质。

4. 发明申请

US20100330762A1 METHOD FOR FORMING BIT LINES FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于形成半导体器件的位线的方法
公开(公告)号：US20100330762A1
公开(公告)日：2010-12-30
申请号：US12880541
申请日：2010-09-13
申请人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
发明人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A memory device includes a number of memory cells and a number of bit lines. Each of the bit lines includes a first region having a first width and a first depth and a second region having a second width and a second depth, where the first width is less than the second width. The first region may include an n-type impurity and the second region may include a p-type impurity,
摘要翻译：存储器件包括多个存储器单元和多个位线。每个位线包括具有第一宽度和第一深度的第一区域和具有第二宽度和第二深度的第二区域，其中第一宽度小于第二宽度。第一区域可以包括n型杂质，第二区域可以包括p型杂质，

5. 发明授权

US06962849B1 Hard mask spacer for sublithographic bitline 有权
标题翻译：用于亚光刻位线的硬掩模垫片
公开(公告)号：US06962849B1
公开(公告)日：2005-11-08
申请号：US10729732
申请日：2003-12-05
申请人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh , Mark T. Ramsbey , Ashok M. Khathuria
发明人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh , Mark T. Ramsbey , Ashok M. Khathuria
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Spacers are utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。在形成过程中使用间隔物来减小存储器中的掩埋位线的尺寸，这适用于存储用于计算机等的数据。较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。

6. 发明授权

US06872609B1 Narrow bitline using Safier for mirrorbit 有权
标题翻译：使用Safier进行镜像位的窄位线
公开(公告)号：US06872609B1
公开(公告)日：2005-03-29
申请号：US10755430
申请日：2004-01-12
申请人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh
发明人： Tazrien Kamal , Weidong Qian , Kouros Ghandehari , Taraneh Jamali-Beh
IPC分类号： H01L21/337 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. A Safier material is utilized in the formation process to reduce the size of buried bitlines in the memory, which is suitable for use in storing data for computers and the like. The smaller (e.g., narrower) bitlines facilitate increased packing densities while maintaining an effective channel length between the bitlines. The separation between the bitlines allows dual bits that are stored above the channel within a charge trapping layer to remain sufficiently separated so as to not interfere with one another. In this manner, one bit can be operated on (e.g., for read, write or erase operations) without substantially or adversely affecting the other bit. Additionally, bit separation is preserved and leakage currents, cross talk, as well as other adverse effects that can result from narrow channels are mitigated, and the memory device is allowed to operate as desired.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。在形成过程中采用Safier材料以减小存储器中的埋置位线的尺寸，其适用于存储用于计算机等的数据。较小（例如较窄）的位线有助于增加打包密度，同时保持位线之间的有效通道长度。位线之间的间隔允许存储在电荷俘获层内的通道上方的双位保持充分分离，以便彼此不干扰。以这种方式，一个位可以被操作（例如，用于读取，写入或擦除操作）而基本上或不利地影响另一个位。此外，保留位分离，并且减轻了可能由窄通道产生的漏电流，串扰以及其他不利影响，并且允许存储器件根据需要进行操作。

7. 发明授权

US07176113B1 LDC implant for mirrorbit to improve Vt roll-off and form sharper junction 有权
标题翻译： LDC植入物用于镜像，以改善Vt滚降并形成更清晰的接合
公开(公告)号：US07176113B1
公开(公告)日：2007-02-13
申请号：US10862636
申请日：2004-06-07
申请人： Nga-Ching Alan Wong , Weidong Qian , Sameer Haddad , Mark Randolph , Mark Ramsbey , Tazrien Kamal
发明人： Nga-Ching Alan Wong , Weidong Qian , Sameer Haddad , Mark Randolph , Mark Ramsbey , Tazrien Kamal
IPC分类号： H01L21/425
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.
摘要翻译：本发明涉及在形成存储器件中实施轻掺杂通道（LDC）植入物以改善Vt滚降等。轻掺杂通道有助于保持通道完整性，使得阈值电压（Vt）可以保持在相对稳定的水平，从而减轻Vt滚降。 LDC还有助于减少掩埋位线宽度，从而使位线更靠近在一起。因此，可以在相同或更小的区域内形成或“包装”更多的装置。

8. 发明授权

US07256141B1 Interface layer between dual polycrystalline silicon layers 有权
标题翻译：双层多晶硅层之间的界面层
公开(公告)号：US07256141B1
公开(公告)日：2007-08-14
申请号：US11135492
申请日：2005-05-24
申请人： Mark T. Ramsbey , Weidong Qian , Mark Chang , Eric Paton
发明人： Mark T. Ramsbey , Weidong Qian , Mark Chang , Eric Paton
IPC分类号： H01L21/31
CPC分类号： H01L27/115 , H01L27/11568
摘要： A structure interfaces dual polycrystalline silicon layers. The structure includes a first layer of polycrystalline silicon and a metal interface layer formed on a surface of the first layer of polycrystalline silicon. The structure further includes a second layer of polycrystalline silicon formed on a surface of the interface layer.
摘要翻译： A结构接双晶硅层。该结构包括第一层多晶硅和形成在第一多晶硅层的表面上的金属界面层。该结构还包括形成在界面层的表面上的第二层多晶硅。

9. 发明授权

US07432178B2 Bit line implant 有权
标题翻译：位线植入
公开(公告)号：US07432178B2
公开(公告)日：2008-10-07
申请号：US11254769
申请日：2005-10-21
申请人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
发明人： Angela T. Hui , Jean Yang , Yu Sun , Mark T. Ramsbey , Weidong Qian
IPC分类号： H01L21/04
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.
摘要翻译：公开了一种用于执行位线植入的方法。该方法包括在半导体器件的氧化物 - 氮化物 - 氧化物堆叠上形成一组结构。该组结构的每个结构包括多晶硅部分和硬掩模部分。该组结构的第一结构与该组结构的第二结构分开小于100纳米。该方法还包括使用第一结构和第二结构来隔离位线植入物的半导体器件的一部分。

10. 发明授权

US07307027B1 Void free interlayer dielectric 有权
标题翻译：无空隙层间电介质
公开(公告)号：US07307027B1
公开(公告)日：2007-12-11
申请号：US11201378
申请日：2005-08-11
申请人： Minh Van Ngo , Alexander Nickel , Hieu Pham , Jean Yang , Hirokazu Tokuno , Weidong Qian
发明人： Minh Van Ngo , Alexander Nickel , Hieu Pham , Jean Yang , Hirokazu Tokuno , Weidong Qian
IPC分类号： H01L21/31
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02274 , H01L21/02304 , H01L21/76837 , H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method of forming a dielectric between memory cells in a device includes forming multiple memory cells, where a gap is formed between each of the multiple memory cells. The method further includes performing a high density plasma deposition (HDP) process to fill at least a portion of the gap between each of the multiple memory cells with a dielectric material.
摘要翻译：在器件中的存储器单元之间形成电介质的方法包括形成多个存储器单元，其中在多个存储器单元中的每一个之间形成间隙。该方法还包括执行高密度等离子体沉积（HDP）工艺以用电介质材料填充每个多个存储器单元之间的间隙的至少一部分。

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