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1. 发明授权

US07176113B1 LDC implant for mirrorbit to improve Vt roll-off and form sharper junction 有权
标题翻译： LDC植入物用于镜像，以改善Vt滚降并形成更清晰的接合
公开(公告)号：US07176113B1
公开(公告)日：2007-02-13
申请号：US10862636
申请日：2004-06-07
申请人： Nga-Ching Alan Wong , Weidong Qian , Sameer Haddad , Mark Randolph , Mark Ramsbey , Tazrien Kamal
发明人： Nga-Ching Alan Wong , Weidong Qian , Sameer Haddad , Mark Randolph , Mark Ramsbey , Tazrien Kamal
IPC分类号： H01L21/425
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or “packed” within the same or a smaller area.
摘要翻译：本发明涉及在形成存储器件中实施轻掺杂通道（LDC）植入物以改善Vt滚降等。轻掺杂通道有助于保持通道完整性，使得阈值电压（Vt）可以保持在相对稳定的水平，从而减轻Vt滚降。 LDC还有助于减少掩埋位线宽度，从而使位线更靠近在一起。因此，可以在相同或更小的区域内形成或“包装”更多的装置。

2. 发明授权

US06989320B2 Bitline implant utilizing dual poly 有权
标题翻译：利用双重聚合物的位线植入
公开(公告)号：US06989320B2
公开(公告)日：2006-01-24
申请号：US10843289
申请日：2004-05-11
申请人： Weidong Qian , Mark Ramsbey , Jean Yee-Mei Yang , Sameer Haddad
发明人： Weidong Qian , Mark Ramsbey , Jean Yee-Mei Yang , Sameer Haddad
IPC分类号： H01L21/425
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许以比常规位线更少的能量和更浅的深度形成掩埋位线，以节省资源和空间，并且改善Vt滚降。氧化物材料也形成在掩埋位线上以改善（例如，增加）位线和字线之间的击穿电压，从而允许编程和擦除电荷之间的更大区分，并且更可靠的结果数据存储。该方法还有助于减少掩埋位线宽度，从而允许位线更靠近地形成。因此，更多的设备可以在相同或较小的区域内“打包”。

3. 发明申请

US20050255651A1 Bitline implant utilizing dual poly 有权
标题翻译：利用双重聚合物的位线植入
公开(公告)号：US20050255651A1
公开(公告)日：2005-11-17
申请号：US10843289
申请日：2004-05-11
申请人： Weidong Qian , Mark Ramsbey , Jean-Yee-Mei Yang , Sameer Haddad
发明人： Weidong Qian , Mark Ramsbey , Jean-Yee-Mei Yang , Sameer Haddad
IPC分类号： H01L21/8246 , H01L27/115 , H01L21/4763
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be “packed” within the same or a smaller area.
摘要翻译：本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。该过程允许以比常规位线更少的能量和更浅的深度形成掩埋位线，以节省资源和空间，并且改善Vt滚降。氧化物材料也形成在掩埋位线上以改善（例如，增加）位线和字线之间的击穿电压，从而允许编程和擦除电荷之间的更大区分，并且更可靠的结果数据存储。该方法还有助于减少掩埋位线宽度，从而允许位线更靠近地形成。因此，更多的设备可以在相同或较小的区域内“打包”。

4. 发明授权

US06958272B2 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
标题翻译：袖珍种植体用于SONOS存储器单元的互补位干扰改进和充电改进
公开(公告)号：US06958272B2
公开(公告)日：2005-10-25
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
发明人： Emmanuil H. Lingunis , Nga-Ching Alan Wong , Sameer Haddad , Mark W. Randolph , Mark T. Ramsbey , Ashot Melik-Martirosian , Edward F. Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.
摘要翻译：公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。然后执行位线注入以在衬底内建立掩埋位线。然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

5. 发明申请

US20050153508A1 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
公开(公告)号：US20050153508A1
公开(公告)日：2005-07-14
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
发明人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

6. 发明授权

US06252276B1 Non-volatile semiconductor memory device including assymetrically nitrogen doped gate oxide 有权
标题翻译：非易失性半导体存储器件包括非均匀氮掺杂的栅极氧化物
公开(公告)号：US06252276B1
公开(公告)日：2001-06-26
申请号：US09377183
申请日：1999-08-19
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L2978
CPC分类号： H01L21/28202 , H01L21/28273 , H01L29/518 , H01L29/66825
摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.
摘要翻译：提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

7. 发明授权

US5972751A Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device 有权
标题翻译：在非易失性半导体存储器件中将氮引入隧道氧化物的方法和装置
公开(公告)号：US5972751A
公开(公告)日：1999-10-26
申请号：US143090
申请日：1998-08-28
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/51
CPC分类号： H01L21/28202 , H01L21/28273 , H01L29/518 , H01L29/66825
摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.
摘要翻译：提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

8. 发明授权

US06989319B1 Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices 有权
标题翻译：在非易失性半导体存储器件中形成富氮区的方法
公开(公告)号：US06989319B1
公开(公告)日：2006-01-24
申请号：US10718707
申请日：2003-11-24
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L21/265
CPC分类号： H01L21/265 , H01L21/28176 , H01L21/28273
摘要： Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer. Consequently, the polysilicon feature has a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The migration of nitrogen further forms a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region. The contiguous reduced-nitrogen region has a lower concentration of nitrogen than does the first nitrogen-rich region and the second nitrogen-rich region. The first nitrogen-rich region has been found to reduce electron trapping within the polysilicon feature. Thus, for example, in a non-volatile memory device wherein the polysilicon feature is a floating gate, false programming of the memory device can be significantly avoided by reducing the number of trapped electrons in the floating gate.
摘要翻译：提供了用于显着减少具有多晶硅特征和上覆电介质层的半导体器件中的电子俘获的方法和装置。所述方法和装置在靠近覆盖的介电层的界面附近使用多晶硅特征内的富氮区域。所述方法包括通过至少部分上覆介质层选择性地注入氮离子并进入多晶硅特征以在多晶硅特征内形成初始氮浓度分布。接下来，将多晶硅特征中的温度升高到足够高的温度，例如使用快速热退火（RTA）技术，其使得初始氮浓度分布由于大部分氮朝着界面迁移而改变与上层电介质层或与下层的界面。因此，多晶硅特征具有在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域。氮的迁移进一步形成位于第一富氮区和第二富氮区之间的连续的还原氮区。连续的还原氮区域具有比第一富氮区域和第二富氮区域低的氮浓度。已发现第一富氮区域减少多晶硅特征内的电子俘获。因此，例如，在其中多晶硅特征是浮动栅极的非易失性存储器件中，可以通过减少浮置栅极中的俘获电子的数量来显着地避免存储器件的伪编程。

9. 发明授权

US06410956B1 Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 有权
标题翻译：使用间隔物补偿植入物损伤并减少闪存装置中的横向扩散的方法和系统
公开(公告)号：US06410956B1
公开(公告)日：2002-06-25
申请号：US09478864
申请日：2000-01-07
申请人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
发明人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
IPC分类号： H01L2976
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.
摘要翻译：公开了一种在半导体上提供存储单元的系统和方法。在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。至少一个栅极堆叠具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入存放至少一个栅极堆叠具有边缘。所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个在间隔物沉积之后在半导体中的漏极注入。至少一个门具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

10. 发明申请

US20050077567A1 Memory cell array with staggered local inter-connect structure 失效
标题翻译：具有交错局部互连结构的存储单元阵列
公开(公告)号：US20050077567A1
公开(公告)日：2005-04-14
申请号：US10685044
申请日：2003-10-14
申请人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
发明人： Mark Randolph , Sameer Haddad , Timothy Thurgate , Richard Fastow
IPC分类号： G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0483 , H01L27/115 , H01L27/11521
摘要： A memory cell array comprises a two dimensional array of memory cells fabricated on a semiconductor substrate. The memory cells are arranged in a plurality of rows and a plurality columns. Each column of memory cells comprising a plurality of alternating channel regions and source/drain regions. A conductive interconnect is positioned above each source/drain region and coupled to only one other source/drain region. The one other source/drain region is in a second column that is adjacent to the column. The conductive interconnects are positioned such that every other conductive interconnect connects to the adjacent column to a right side of the column and every other conductive interconnect connects to adjacent column to the left side of the column. A plurality of source/drain control lines extends between adjacent columns of memory cells and electrically couples to each conductive interconnect that couples between the adjacent columns.
摘要翻译：存储单元阵列包括在半导体衬底上制造的存储器单元的二维阵列。存储单元布置成多行和多列。每列存储单元包括多个交替沟道区和源极/漏极区。导电互连位于每个源极/漏极区域上方并且仅耦合到另一个源极/漏极区域。另一个源/漏区位于与该列相邻的第二列中。导电互连被定位成使得每隔一个导电布线连接到列的右侧的相邻列，并且每隔一个导电布线连接到列的左侧的相邻列。多个源极/漏极控制线在相邻列的存储器单元之间延伸，并且电耦合到在相邻列之间耦合的每个导电互连。

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