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1. 发明授权

US06252806B1 Multi-generator, partial array Vt tracking system to improve array retention time 失效
标题翻译：多发生器，部分阵列Vt跟踪系统，提高阵列保留时间
公开(公告)号：US06252806B1
公开(公告)日：2001-06-26
申请号：US09579749
申请日：2000-05-26
申请人： Wayne F. Ellis , Louis L. Hsu , Brian L. Ji , Yujon Li , Oliver Weinfurtner
发明人： Wayne F. Ellis , Louis L. Hsu , Brian L. Ji , Yujon Li , Oliver Weinfurtner
IPC分类号： G11C1604
CPC分类号： G11C8/08 , G11C5/146 , G11C5/147 , G11C11/4074 , G11C11/4078 , G11C2207/104
摘要： Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.
摘要翻译：通过使用以一小部分监视晶体管阈值电压跟踪的偏置电压调节来获得改进的晶体管阵列器件性能。电路和方法对于改善诸如DRAM和嵌入式DRAM的晶体管阵列器件的性能特别有用。这些优点是特别是当通过至少一个监视晶体管的实际阈值电压的一部分进行跟踪来调节通常提供给阵列的至少两个偏置电压时。性能改进包括改进的可靠性，更宽的操作偏置条件，降低的功耗以及（在存储器单元的情况下）改进的保留时间。

2. 发明授权

US06538932B2 Timing circuit and method for a compilable DRAM 有权
标题翻译：可编程DRAM的定时电路和方法
公开(公告)号：US06538932B2
公开(公告)日：2003-03-25
申请号：US09880598
申请日：2001-06-13
申请人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
发明人： Wayne F. Ellis , John A. Fifield , Louis L. Hsu
IPC分类号： G11C700
CPC分类号： G11C11/4096 , G11C7/1051 , G11C7/22 , G11C11/4076 , G11C2207/2281
摘要： A semiconductor memory is disclosed, the memory comprising: a memory cell adapted to store a bit; a wordline and a bitline coupled to the memory cell; a primary sense amplifier coupled to the bitline to receive a signal representing the stored bit when the wordline is active; a wordline driver coupled to activate the wordline; and a primary delay device adapted to produce a first delay selected from a range of selectable delays, the primary delay device adapted to compensate for signal propagation delay along the wordline.
摘要翻译：公开了一种半导体存储器，所述存储器包括：适于存储位的存储器单元; 耦合到存储器单元的字线和位线; 当所述字线有效时，耦合到所述位线的初级读出放大器接收表示存储位的信号; 耦合以激活字线的字线驱动器; 以及适于产生从可选延迟的范围中选择的第一延迟的主延迟装置，所述主延迟装置适于补偿沿着字线的信号传播延迟。

3. 发明授权

US06452855B1 DRAM array interchangeable between single-cell and twin-cell array operation 失效
标题翻译： DRAM单元与双电池阵列的操作可互换
公开(公告)号：US06452855B1
公开(公告)日：2002-09-17
申请号：US09755868
申请日：2001-01-05
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： H01L27118
CPC分类号： G11C7/1045 , G11C7/1006 , G11C11/4091 , G11C11/4096 , G11C11/4097
摘要： A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
摘要翻译：提供能够在用于以单电池或双电池阵列格式存储数据的单电池和双电池阵列操作之间互换的DRAM阵列。优选地，DRAM阵列在一个操作模式期间以单个单元阵列格式操作，并且DRAM阵列在另一个操作模式期间以双电池阵列格式操作。包括开关电路用于单电池和双电池阵列操作之间的互换，反之亦然。还提供了用于将DRAM阵列中存储的数据从单小区转换为双小区阵列格式的方法，反之亦然。

4. 发明授权

US06337595B1 Low-power DC voltage generator system 有权
公开(公告)号：US06337595B1
公开(公告)日：2002-01-08
申请号：US09627599
申请日：2000-07-28
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
IPC分类号： G05F302
CPC分类号： G05F3/265
摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

5. 发明授权

US07305515B2 Performance optimizing compiler for building a compiled DRAM 失效
标题翻译：用于构建编译的DRAM的性能优化编译器
公开(公告)号：US07305515B2
公开(公告)日：2007-12-04
申请号：US09793037
申请日：2001-02-26
申请人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Rajiv V. Joshi , John A. Fifield , Wayne F. Ellis
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F17/5045
摘要： A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.
摘要翻译：提供了一种用于编译DRAM宏的至少一个阵列或存储体单元的编译器，使得包括循环时间，访问时间，建立时间在内的电性能以及其他特性被优化。编译器根据输入的信息编译DRAM宏。编译器接收DRAM宏的输入容量和配置。编译器算法确定创建输入容量的DRAM宏所需的字数和位线数。编译器算法通过根据字线和位线的数量正确配置DRAM宏的支持单元来优化DRAM宏的周期时间和访问时间。

6. 发明授权

US06507237B2 Low-power DC voltage generator system 失效
公开(公告)号：US06507237B2
公开(公告)日：2003-01-14
申请号：US10039874
申请日：2002-01-03
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton , Wayne F. Ellis , Jeffrey H. Dreibelbis
IPC分类号： G05F110
CPC分类号： G05F3/265
摘要： A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt. A one-volt negative voltage pump circuit is also included for pumping the voltages of at least one corresponding charge pump circuit, even when an operating voltage of the DC generator system is at or near one-volt. The DC voltage generator system is specifically designed to be implemented within battery-operated devices having at least one memory unit. The low-power consumption feature of the DC voltage generator system extends battery lifetime and data retention time of the cells of the at least one memory unit.

7. 发明授权

US06737907B2 Programmable DC voltage generator system 失效
标题翻译：可编程直流电压发生器系统
公开(公告)号：US06737907B2
公开(公告)日：2004-05-18
申请号：US09898328
申请日：2001-07-03
申请人： Louis L. Hsu , Li-Kong Wang , John Atkinson Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Li-Kong Wang , John Atkinson Fifield , Wayne F. Ellis
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2001/0012 , H02M2001/0025
摘要： A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.
摘要翻译：一种具有用于控制电压发生器系统的控制电路的编程电路的数字可编程直流电压发生器系统。编程电路接收输入控制信号，处理输入控制信号，并将输出控制信号产生到电压发生器系统的控制电路，用于根据输入控制信号控制控制电路。控制电路包括限幅电路和振荡电路。输出控制信号控制至少一个限制电路，用于在达到目标输出电压时使振荡器电路无效，以及用于控制振荡器电路的泵送速度的振荡器电路。

8. 发明授权

US08198174B2 Air channel interconnects for 3-D integration 有权
标题翻译：空气通道互连用于3-D集成
公开(公告)号：US08198174B2
公开(公告)日：2012-06-12
申请号：US12536176
申请日：2009-08-05
申请人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
发明人： Louis L. Hsu , Brian L. Ji , Fei Liu , Conal E. Murray
IPC分类号： H01L21/44
CPC分类号： H01L23/467 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional (3D) chip stack structure and method of fabricating the structure thereof are provided. The 3D chip stack structure includes a plurality of vertically stacked chips which are interconnected and bonded together, wherein each of the vertically stacked chips include one or more IC device strata. The 3D chip stack structure further includes an air channel interconnect network embedded within the chip stack structure, and wherein the air channel interconnect network is formed in between at least two wafers bonded to each other of the vertically stacked wafers and in between at least two bonded wafers of the vertically stacked wafers at a bonding interface thereof. In addition, the 3D chip stack structure further includes one or more openings in a peripheral region of the chip stack structure that lead into and out of the air channel interconnect network, so that air can flow into and out of the air channel interconnect network through the one or more openings to remove heat from the chip stack structure.
摘要翻译：提供三维（3D）芯片堆叠结构及其结构的制造方法。 3D芯片堆叠结构包括互连并结合在一起的多个垂直堆叠的芯片，其中每个垂直堆叠的芯片包括一个或多个IC器件层。 3D芯片堆叠结构还包括嵌入在芯片堆叠结构内的空气通道互连网络，并且其中空气通道互连网络形成在至少两个晶片之间，所述至少两个晶片彼此接合在垂直堆叠的晶片之间，并且在至少两个结合在其接合界面处的垂直堆叠的晶片的晶片。此外，3D芯片堆叠结构还包括在芯片堆叠结构的外围区域中的一个或多个开口，其引入和流出空气通道互连网络，使得空气可以流入和流出空气通道互连网络，通过一个或多个开口以从芯片堆叠结构移除热量。

9. 发明授权

US07355872B2 Segmented content addressable memory architecture for improved cycle time and reduced power consumption 有权
标题翻译：分段内容可寻址内存架构，可提高周期时间并降低功耗
公开(公告)号：US07355872B2
公开(公告)日：2008-04-08
申请号：US10673801
申请日：2003-09-29
申请人： Louis L. Hsu , Brian L. Ji , Li-Kong Wang
发明人： Louis L. Hsu , Brian L. Ji , Li-Kong Wang
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (“CAM”) system includes a plurality of segments arranged in an array, wherein each of the plurality of segments includes a plurality of CAM cells, each of the plurality of CAM cells includes a wordline, a matchline and a sinkline, the wordline being shared by all of the cells in the same row, the matchline and sinkline being shared by all of the cells in the same segment; and a corresponding method of searching within a CAM system includes providing an input word to the CAM system, comparing a portion of the input word in a segment of the CAM system, and propagating a mismatch to obviate the need for comparison in other segments of the CAM system.
摘要翻译：内容可寻址存储器（“CAM”）系统包括以阵列排列的多个段，其中多个段中的每个段包括多个CAM单元，多个CAM单元中的每一个包括字线，匹配线和下沉线，该字线由同一行中的所有单元共享，匹配线和汇线由同一段中的所有单元共享; 并且相应的在CAM系统内搜索的方法包括向CAM系统提供输入字，比较CAM系统的片段中的输入字的一部分，并且传播不匹配，以避免在 CAM系统。

10. 发明授权

US07216284B2 Content addressable memory having reduced power consumption 有权
标题翻译：内容可寻址存储器具有降低的功耗
公开(公告)号：US07216284B2
公开(公告)日：2007-05-08
申请号：US10145018
申请日：2002-05-15
申请人： Louis L. Hsu , Brian L. Ji , Li-Kong Wang
发明人： Louis L. Hsu , Brian L. Ji , Li-Kong Wang
IPC分类号： G11C29/00
CPC分类号： G11C15/04 , G11C15/043
摘要： A content addressable memory (CAM). A data portion of the CAM array includes word data storage. Each word line includes CAM cells (dynamic or static) in the data portion and a common word match line. An error correction (e.g., parity) portion of the CAM array contains error correction cells for each word line. Error correction cells at each word line are connected to an error correction match line. A match on an error correction match line enables precharging a corresponding data match line. Only data on word lines with a corresponding match on an error correction match line are included in a data compare. Precharge power is required only for a fraction (inversely exponentially proportional to the bit length of error correction employed) of the full array.
摘要翻译：内容可寻址存储器（CAM）。 CAM阵列的数据部分包括字数据存储。每个字线包括数据部分中的CAM单元（动态或静态）和公共字匹配线。 CAM阵列的纠错（例如，奇偶校验）部分包含每个字线的纠错单元。每个字线处的误差校正单元连接到纠错匹配线。纠错匹配线上的匹配可以对相应的数据匹配线进行预充电。在数据比较中仅包括在纠错匹配行上具有对应匹配的字线上的数据。预充电功率只需要一个分数（与所使用的误差校正的位长度成反比成正比）的整数组。

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