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    • 5. 发明申请
    • NITRIDE SEMICONDUCTOR DEVICE
    • 氮化物半导体器件
    • US20130062671A1
    • 2013-03-14
    • US13420559
    • 2012-03-14
    • Wataru SAITOYasunobu SaitoHidetoshi FujimotoAkira YoshiokaTestsuya Ohno
    • Wataru SAITOYasunobu SaitoHidetoshi FujimotoAkira YoshiokaTestsuya Ohno
    • H01L29/78
    • H01L29/7786H01L29/1066H01L29/1075H01L29/1087H01L29/2003H01L29/4236H01L29/7783
    • A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a conductive substrate, a first electrode, a second electrode, and a control electrode. The second semiconductor layer is directly bonded to the first semiconductor layer. The conductive substrate is provided on and electrically connected to the first semiconductor layer. The first electrode and the second electrode are provided on and electrically connected to a surface of the second semiconductor layer on a side opposite to the first semiconductor layer. The control electrode is provided on the surface of the second semiconductor layer between the first electrode and the second electrode. The first electrode is electrically connected to a drain electrode of a MOSFET formed of Si. The control electrode is electrically connected to a source electrode of the MOSFET. The conductive substrate is electrically connected to a gate electrode of the MOSFET.
    • 氮化物半导体器件包括第一半导体层,第二半导体层,导电衬底,第一电极,第二电极和控制电极。 第二半导体层直接接合到第一半导体层。 导电基板设置在电连接到第一半导体层上。 第一电极和第二电极设置在与第一半导体层相对的一侧上与第二半导体层的表面电连接。 控制电极设置在第一电极和第二电极之间的第二半导体层的表面上。 第一电极电连接到由Si形成的MOSFET的漏电极。 控制电极与MOSFET的源电极电连接。 导电基板电连接到MOSFET的栅电极。
    • 8. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120012929A1
    • 2012-01-19
    • US13051987
    • 2011-03-18
    • Wataru SAITOSyotaro OnoShunji TaniuchiMiho WatanabeHiroaki Yamashita
    • Wataru SAITOSyotaro OnoShunji TaniuchiMiho WatanabeHiroaki Yamashita
    • H01L29/78
    • H01L29/7813H01L29/0865H01L29/0878H01L29/1095H01L29/407H01L29/42372H01L29/66734
    • According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.
    • 根据一个实施例,半导体器件包括第一导电类型的第一半导体层,第一导电类型的第二半导体层,第二导电类型的第三半导体层,第二导电类型的第四半导体层, 第一导电类型的第五半导体层,第一导电类型的控制电极,第一主电极,第二主电极和第六半导体层。 第二半导体层和第三半导体层在与第一半导体层的主表面大致平行的方向上交替地设置在第一半导体层上。 第四半导体层设置在第二半导体层和第三半导体层上。 第五半导体层选择性地设置在第四半导体层的表面上。 控制电极通过绝缘膜设置在沟槽中。 沟槽从第五半导体层的表面穿过第四半导体层并且与第二半导体层接触。 第一主电极连接到第一半导体层。 第二主电极连接到第四半导体层和第五半导体层。 第六半导体层设置在第四半导体层和第二半导体层之间。 第六半导体层的杂质浓度高于第二半导体层的杂质浓度。
    • 9. 发明申请
    • POWER SEMICONDUCTOR DEVICE
    • 功率半导体器件
    • US20100308399A1
    • 2010-12-09
    • US12728823
    • 2010-03-22
    • Wataru SAITOSyotaro ONOMunehisa YABUZAKINana HATANOMiho WATANABE
    • Wataru SAITOSyotaro ONOMunehisa YABUZAKINana HATANOMiho WATANABE
    • H01L29/78
    • H01L29/7802H01L29/0619H01L29/0626H01L29/0634H01L29/0657H01L29/0696H01L29/0878H01L29/1095H01L29/4236H01L29/42368H01L29/4238H01L29/7808H01L29/7811H01L29/7828
    • A power semiconductor device includes: a first semiconductor layer of the first conduction type; second semiconductor layers of the first conduction type and third semiconductor layers of the second conduction type alternately provided transversely on the first semiconductor layer; fourth semiconductor layers of the second conduction type provided on the surfaces of the third semiconductor layers; fifth semiconductor layers of the first conduction type provided selectively on the surfaces of the fourth semiconductor layer; sixth semiconductor layers of the second conduction type and seventh semiconductor layers of the first conduction type alternately provided transversely on the second and the third semiconductor layers; a first main electrode electrically connected to the first semiconductor layer; an insulation film provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers; a control electrode provided on the fourth semiconductor layers, the sixth semiconductor layers and the seventh semiconductor layers via the insulation film; and a second main electrode joined to the surfaces of the fourth semiconductor layers and the fifth semiconductor layers, the sixth semiconductor layers being connected to the fourth semiconductor layers and to at least one of the third semiconductor layers, which is provided between two of the fourth semiconductor layers, and an impurity concentration of the third semiconductor layers provided below the sixth semiconductor layers being higher than an impurity concentration of the third semiconductor layers provided under the fourth semiconductor layers.
    • 功率半导体器件包括:第一导电类型的第一半导体层; 第一导电类型的第二半导体层和第二导电类型的第三半导体层交替地设置在第一半导体层上; 设置在第三半导体层的表面上的第二导电类型的第四半导体层; 选择性地在第四半导体层的表面上提供第一导电类型的第五半导体层; 第二导电类型的第六半导体层和第一导电类型的第七半导体层交替地设置在第二和第三半导体层上; 电连接到第一半导体层的第一主电极; 设置在第四半导体层,第六半导体层和第七半导体层上的绝缘膜; 设置在第四半导体层上的控制电极,第六半导体层和第七半导体层经由绝缘膜; 以及与所述第四半导体层和所述第五半导体层的表面接合的第二主电极,所述第六半导体层与所述第四半导体层连接,并且至少一个所述第三半导体层设置在所述第四半导体层 并且设置在第六半导体层下方的第三半导体层的杂质浓度高于设置在第四半导体层下方的第三半导体层的杂质浓度。