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1. 发明申请

US20130248931A1 NITRIDE SEMICONDUCTOR DEVICE 失效
标题翻译：氮化物半导体器件
公开(公告)号：US20130248931A1
公开(公告)日：2013-09-26
申请号：US13599951
申请日：2012-08-30
申请人： Wataru SAITO , Yasunobu SAITO , Hidetoshi FUJIMOTO , Akira YOSHIOKA , Tetsuya OHNO , Toshiyuki NAKA
发明人： Wataru SAITO , Yasunobu SAITO , Hidetoshi FUJIMOTO , Akira YOSHIOKA , Tetsuya OHNO , Toshiyuki NAKA
IPC分类号： H01L29/778
CPC分类号： H01L27/0727 , H01L21/8252 , H01L27/0207 , H01L27/0605 , H01L27/0629 , H01L29/0619 , H01L29/1066 , H01L29/2003 , H01L29/41758 , H01L29/7786 , H01L29/872 , H01L2924/0002 , H02M3/155 , H02M3/33569 , H02M2001/007 , H01L2924/00
摘要： According to one embodiment, a nitride semiconductor device has an electroconductive substrate, a first nitride semiconductor layer provided directly on the electroconductive substrate or provided on the electroconductive substrate through a buffer layer and formed of a non-doped nitride semiconductor, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, first and second element isolation insulating layers, and a frame electrode. The frame electrode is electrically connected to the source electrode and the electroconductive substrate, and surrounds outer peripheries of the heterojunction field effect transistor and the Schottky barrier diode.
摘要翻译：根据一个实施例，氮化物半导体器件具有导电衬底，第一氮化物半导体层，直接设置在导电衬底上，或通过缓冲层设置在导电衬底上，并由非掺杂氮化物半导体形成，第二氮化物半导体层设置在所述第一氮化物半导体层上并且由具有比所述第一氮化物半导体层宽的带隙的非掺杂或n型氮化物半导体形成的异质结场效应晶体管具有源电极，漏电极和栅电极，具有阳极电极和阴极电极的肖特基势垒二极管，第一和第二元件隔离绝缘层以及框架电极。框电极电连接到源电极和导电衬底，并且包围异质结场效应晶体管和肖特基势垒二极管的外周。

2. 发明申请

US20130082261A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20130082261A1
公开(公告)日：2013-04-04
申请号：US13612200
申请日：2012-09-12
申请人： Wataru SAITO , Syotaro ONO , Toshiyuki NAKA , Shunji TANIUCHI , Hiroaki YAMASHITA
发明人： Wataru SAITO , Syotaro ONO , Toshiyuki NAKA , Shunji TANIUCHI , Hiroaki YAMASHITA
IPC分类号： H01L27/088
CPC分类号： H01L27/0629 , H01L27/0727 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/42372 , H01L29/7803 , H01L29/7804 , H01L29/7805 , H01L29/7806 , H01L29/7808 , H01L29/7813 , H01L29/7827 , H01L29/868 , H01L29/872
摘要： A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.
摘要翻译：一种半导体器件，包括：金属氧化物半导体场效应晶体管，包括：半导体衬底，包括第一导电类型的第一半导体层; 第二导电类型的第二半导体层，在深度方向上从半导体衬底的一个表面延伸并且彼此具有空间; 第一二极管，包括在半导体衬底的一个表面侧中与第二半导体层接触的第二导电类型的第五半导体层，第一半导体层和第二半导体层; 并且所述第二二极管的阳极连接到所述第一二极管的阳极。

3. 发明申请

US20070257653A1 SWITCHING POWER CIRCUIT AND POWER CONTROL METHOD 失效
标题翻译：切换电源电路和功率控制方法
公开(公告)号：US20070257653A1
公开(公告)日：2007-11-08
申请号：US11742895
申请日：2007-05-01
申请人： Toshiyuki NAKA
发明人： Toshiyuki NAKA
IPC分类号： G05F1/00
CPC分类号： H02M3/157
摘要： A switching power circuit having a counter which periodically counts a value between a first value and a second value, a determining unit which continuously determines a third value between the first value and the second value, based on a voltage difference between an output voltage and a reference voltage, a driving unit which alternately switches a first switching element and a second switching element, base on a small and large relation between a counting value of the counter and the third value, and a control unit which resets the counting value of the counter to the first value, based on the voltage difference or a current value at the second switching element.
摘要翻译：一种开关电源电路，具有周期性地计数第一值和第二值之间的值的计数器，确定单元，其基于输出电压和第二值之间的电压差连续地确定第一值和第二值之间的第三值参考电压，基于计数器的计数值与第三值之间的小而大的关系交替地切换第一开关元件和第二开关元件的驱动单元以及重置计数器的计数值的控制单元基于第二开关元件处的电压差或电流值来计算第一值。

4. 发明申请

US20090146630A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090146630A1
公开(公告)日：2009-06-11
申请号：US12327118
申请日：2008-12-03
申请人： Toshiyuki NAKA
发明人： Toshiyuki NAKA
IPC分类号： G05F1/10
CPC分类号： H02M3/157 , H02M1/38 , H02M3/1588 , Y02B70/1466
摘要： A semiconductor device includes: a digital control circuit configured to supply two semiconductor switching elements connected in series in a switching power supply circuit with a pulse signal for turning on/off the semiconductor switching elements; and a dead time setting circuit configured to set a dead time in which the two semiconductor switching elements are both turned off. The dead time setting circuit includes: a delay generation circuit including a plurality of delay elements connected in series and having mutually different delay values; and a delay adjustment circuit configured to adjust the delay values of the delay generation circuit so that a setting value of the dead time is determined on basis of correlation between the dead time and the duty cycle of the pulse signal.
摘要翻译：半导体器件包括：数字控制电路，被配置为将开关电源电路中串联连接的两个半导体开关元件与用于接通/断开半导体开关元件的脉冲信号相提供; 以及死区设定电路，其配置为设定两个半导体开关元件都截止的死区时间。死区设置电路包括：延迟产生电路，包括串联连接并具有相互不同延迟值的多个延迟元件; 以及延迟调整电路，被配置为调整延迟产生电路的延迟值，使得基于死区时间和脉冲信号的占空比之间的相关性来确定死区时间的设定值。

5. 发明申请

US20120256607A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20120256607A1
公开(公告)日：2012-10-11
申请号：US13527678
申请日：2012-06-20
申请人： Kazutoshi NAKAMURA , Toru TAKAYAMA , Yuki KAMATA , Akio NAKAGAWA , Yoshinobu SANO , Toshiyuki NAKA
发明人： Kazutoshi NAKAMURA , Toru TAKAYAMA , Yuki KAMATA , Akio NAKAGAWA , Yoshinobu SANO , Toshiyuki NAKA
IPC分类号： G05F1/00
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

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