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1. 发明授权

US5381027A Semiconductor device having a heterojunction and a two dimensional gas as an active layer 失效
标题翻译：具有异质结和二维气体作为有源层的半导体器件
公开(公告)号：US5381027A
公开(公告)日：1995-01-10
申请号：US134622
申请日：1993-10-12
申请人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
发明人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
IPC分类号： H01L21/18 , H01L21/285 , H01L21/331 , H01L21/335 , H01L27/06 , H01L29/737 , H01L29/778 , H01L29/804 , H01L29/784
CPC分类号： H01L29/66318 , H01L21/182 , H01L21/28587 , H01L27/0605 , H01L29/66462 , H01L29/7373 , H01L29/7787
摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.
摘要翻译：本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。这些半导体器件可以降低源极栅极电阻和寄生基极电阻。本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

2. 发明授权

US5258631A Semiconductor device having a two-dimensional electron gas as an active layer 失效
标题翻译：具有二维电子气体作为活性层的半导体装置
公开(公告)号：US5258631A
公开(公告)日：1993-11-02
申请号：US884878
申请日：1992-05-18
申请人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
发明人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
IPC分类号： H01L21/18 , H01L21/285 , H01L21/331 , H01L21/335 , H01L27/06 , H01L29/737 , H01L29/778 , H01L29/06 , H01L29/167 , H01L29/30 , H01L31/072
CPC分类号： H01L29/66318 , H01L21/182 , H01L21/28587 , H01L27/0605 , H01L29/66462 , H01L29/7373 , H01L29/7787
摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.
摘要翻译：本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。前者通过应用其源极和漏极区域的形成来制造通过引入杂质例如通过离子注入引起异质结的紊乱的技术或通过形成由选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。这些半导体器件可以降低源极栅极电阻和寄生基极电阻。本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

3. 发明授权

US5373191A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5373191A
公开(公告)日：1994-12-13
申请号：US998856
申请日：1992-12-30
申请人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
发明人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
IPC分类号： H01L21/285 , H01L21/331 , H01L21/335 , H01L21/337 , H01L21/338 , H01L21/60 , H01L21/8252 , H01L23/485 , H01L29/812 , H01L29/80 , H01L23/48 , H01L29/06 , H01L29/48
CPC分类号： H01L21/76897 , H01L21/28587 , H01L21/8252 , H01L23/485 , H01L29/66318 , H01L29/66462 , H01L29/66863 , H01L29/66871 , H01L29/66924 , H01L29/8128 , H01L2924/0002
摘要： Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors. Such semiconductor devices can readily be produced by forming a gate electrode metal with a self-alignment process using the lift-off method.
摘要翻译：具有凹陷栅电极金属的场效应晶体管的源电极和漏电极金属通过限定凹部的侧壁的绝缘膜直接连接到面向栅电极金属的高杂质浓度半导体层。源电极和漏电极金属可以通过侧绝缘膜设置成面对栅电极金属。通过这种布置，可以降低场效应晶体管的栅电极和另一电极之间的寄生电阻，以降低半导体层与源电极和漏电极之间的接触电阻，以减小凹陷栅电极的电容并且有利地增加源极栅极击穿电压。上述布置特别适用于采用化合物半导体的晶体管，并且还可以应用于场效应晶体管以外的半导体器件。这种半导体器件可以容易地通过使用剥离法形成具有自对准工艺的栅电极金属来制造。

4. 发明授权

US5181087A Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5181087A
公开(公告)日：1993-01-19
申请号：US340471
申请日：1989-04-19
申请人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
发明人： Toshiyuki Usagawa , Yoshinori Imamura , Hidekazu Okuhira , Shigeo Goto , Masayoshi Kobayashi , Shinichiro Takatani
IPC分类号： H01L21/285 , H01L21/331 , H01L21/335 , H01L21/337 , H01L21/338 , H01L21/60 , H01L21/8252 , H01L23/485 , H01L29/812
CPC分类号： H01L21/76897 , H01L21/28587 , H01L21/8252 , H01L23/485 , H01L29/66318 , H01L29/66462 , H01L29/66863 , H01L29/66871 , H01L29/66924 , H01L29/8128 , H01L2924/0002
摘要： Source and drain electrode metals of a field effect transistor having a recessed gate electrode metal are directly connected to a high impurity concentration semiconductor layer which faces the gate electrode metal through an insulator film which defines the side wall of the recess. The source and drain electrode metals may be disposed so as to face the gate electrode metal through the side insulator film. With this arrangement, it is possible to lower the parasitic resistance between the gate electrode and another electrode of the field effect transistor, to lower the contact resistance between a semiconductor layer and the source and drain electrodes, to reduce the capacitance of the recess gate electrode and to increase the source-gate breakdown voltage, advantageously. The above-described arrangement is particularly suitable for a transistor employing a compound semiconductor, and can also be applied to semiconductor devices other than field effect transistors. Such semiconductor devices can readily be produced by forming a gate electrode metal with a self-alignment process using the lift-off method.
摘要翻译：具有凹陷栅电极金属的场效应晶体管的源电极和漏电极金属通过限定凹部的侧壁的绝缘膜直接连接到面向栅电极金属的高杂质浓度半导体层。源电极和漏电极金属可以通过侧绝缘膜设置成面对栅电极金属。通过这种布置，可以降低场效应晶体管的栅电极和另一电极之间的寄生电阻，以降低半导体层与源电极和漏电极之间的接触电阻，以减小凹陷栅电极的电容并且有利地增加源极栅极击穿电压。上述布置特别适用于采用化合物半导体的晶体管，并且还可以应用于场效应晶体管以外的半导体器件。这种半导体器件可以容易地通过使用剥离法形成具有自对准工艺的栅电极金属来制造。

5. 发明授权

US5332910A Semiconductor optical device with nanowhiskers 失效
标题翻译：具有纳米晶须的半导体光学器件
公开(公告)号：US5332910A
公开(公告)日：1994-07-26
申请号：US159343
申请日：1993-11-30
申请人： Keiichi Haraguchi , Kenji Hiruma , Kensuke Ogawa , Toshio Katsuyama , Ken Yamaguchi , Toshiyuki Usagawa , Masamits Yazawa , Toshiaki Masuhara , Gerard P. Morgan , Hiroshi Kakibayashi
发明人： Keiichi Haraguchi , Kenji Hiruma , Kensuke Ogawa , Toshio Katsuyama , Ken Yamaguchi , Toshiyuki Usagawa , Masamits Yazawa , Toshiaki Masuhara , Gerard P. Morgan , Hiroshi Kakibayashi
IPC分类号： G02B6/42 , H01L33/00 , H01L33/24 , H01S3/067 , H01S5/00 , H01S5/02 , H01S5/06 , H01S5/10 , H01S5/12 , H01S5/18 , H01S5/183 , H01S5/223 , H01S5/32 , H01S5/34 , H01S5/40 , H01S5/42 , H01S5/50
CPC分类号： H01L33/24 , B82Y20/00 , G02B6/4202 , H01L33/0062 , H01S5/1228 , H01S5/183 , H01S5/4031 , H01S3/06708 , H01S5/0028 , H01S5/0217 , H01S5/0608 , H01S5/1042 , H01S5/105 , H01S5/18 , H01S5/223 , H01S5/3202 , H01S5/3412 , H01S5/4006 , H01S5/4056 , H01S5/423 , H01S5/5045
摘要： A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.
摘要翻译：半导体发光器件包括多个半导体棒，每个半导体棒具有pn结。半导体棒形成在半导体衬底上，使得多个半导体棒被布置成基本上等于从半导体棒发射的光的波长的整数倍的距离。利用这样的装置，可以实现各种新颖的光学装置，例如阈值电流极小的微腔激光器和不具有阈值的相干发光装置。

6. 发明授权

US4805005A Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US4805005A
公开(公告)日：1989-02-14
申请号：US783086
申请日：1985-10-02
申请人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
发明人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
IPC分类号： H01L21/338 , H01L21/8252 , H01L27/095 , H01L29/10 , H01L29/778 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7787 , H01L21/8252 , H01L29/1029 , H01L29/1075 , H01L29/8122
摘要： A semiconductor device and method of manufacturing the same. The device comprises a first n-type semiconductor layer and a second undoped semiconductor layer between which a hetero-junction is formed, and a third p-type embedded semiconductor layer, a gate metal formed without the exposure to air immediately after the third, second and first semiconductor layer are successively formed, and an external electrode connected with the third p-type embedded semiconductor layer, capable of controlling the carriers in the neighborhood of the hetero-junction. This semiconductor device greatly improves the controllability of the threshold voltage thereof, and provides the gate electrodes of good quality.
摘要翻译：一种半导体器件及其制造方法。该器件包括第一n型半导体层和在其之间形成异质结的第二未掺杂半导体层，以及第三p型嵌入式半导体层，在三分之一之后立即形成不暴露于空气的栅极金属，第二并且连续形成第一半导体层，以及与第三p型嵌入式半导体层连接的能够控制异质结附近的载流子的外部电极。该半导体器件极大地提高了其阈值电压的可控性，并且提供质量好的栅电极。

7. 发明授权

US4710787A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4710787A
公开(公告)日：1987-12-01
申请号：US686691
申请日：1984-12-27
申请人： Toshiyuki Usagawa , Yuichi Ono , Susumu Takahashi
发明人： Toshiyuki Usagawa , Yuichi Ono , Susumu Takahashi
IPC分类号： H01L29/812 , H01L21/338 , H01L29/201 , H01L29/205 , H01L29/68 , H01L29/772 , H01L29/778 , H01L29/80 , H01L29/161 , H01L29/06 , H01L29/12 , H01L29/74
CPC分类号： H01L29/7787 , H01L29/7722
摘要： A semiconductor device is provided comprising a control electrode for forming carriers at a junction interface between first and second layers of different materials and for controlling the carriers, a first electrode which is electronically connected to the carriers, and a second electrode region for taking out the carriers in a direction perpendicular to the junction interface. Since the two-dimensional carriers are caused to flow as a current in the direction perpendicular to a plane on which the carriers exist, a great current can be derived as an operating current.
摘要翻译：提供了一种半导体器件，包括用于在不同材料的第一和第二层之间的结界面处形成载流子并用于控制载流子的控制电极，电连接到载体的第一电极和用于取出载体在垂直于结界面的方向上。由于使二维载流子作为与存在载流子的平面垂直的方向的电流流动，所以能够导出大的电流作为工作电流。

8. 发明授权

US4683487A Heterojunction bipolar transistor 失效
标题翻译：异质结双极晶体管
公开(公告)号：US4683487A
公开(公告)日：1987-07-28
申请号：US795465
申请日：1985-11-06
申请人： Kiichi Ueyanagi , Susumu Takahashi , Toshiyuki Usagawa , Yasunari Umemoto , Toshihisa Tsukada
发明人： Kiichi Ueyanagi , Susumu Takahashi , Toshiyuki Usagawa , Yasunari Umemoto , Toshihisa Tsukada
IPC分类号： H01L21/331 , H01L29/06 , H01L29/20 , H01L29/417 , H01L29/423 , H01L29/73 , H01L29/737 , H01L29/72
CPC分类号： H01L29/0642 , H01L29/41708 , H01L29/42304 , H01L29/73 , H01L29/7371
摘要： A collector lead-out portion and a base lead-out portion are formed so as to oppose to each other in such a manner that active regions including a collector, a base and an emitter are sandwiched therebetween. The collector lead-out portion and the base lead-out portion are formed by ion implantation or selective epitaxial growth. Thus, a planar type heterojunction bipolar transistor capable of a high density of integration is formed.
摘要翻译：以这样的方式形成集电体引出部分和基极引出部分，以便将包括集电极，基极和发射极的有源区夹在其间的方式彼此相对。集电极引出部分和基极引出部分通过离子注入或选择性外延生长形成。因此，形成了具有高密度集成度的平面型异质结双极晶体管。

9. 发明申请

US20120217550A1 GAS SENSOR 有权
标题翻译：气体传感器
公开(公告)号：US20120217550A1
公开(公告)日：2012-08-30
申请号：US13508082
申请日：2010-10-01
申请人： Toshiyuki Usagawa
发明人： Toshiyuki Usagawa
IPC分类号： H01L27/088
CPC分类号： G01N27/4141 , G01N27/4148 , G01N33/005
摘要： A MISFET-type hydrogen gas sensor having low power consumption which can be operated for one year or longer at a low voltage power source (for example, 1.5 to 3 V) is achieved. A sensor FET is formed in a MEMS region 34 where a Si substrate 22 of a SOI substrate is bored, and a heater wiring 32 is arranged so as to be folded between a Pi-Ti—O gate 28 and a source electrode 31S of the sensor FET and between the Pt—Ti—O gate 28 and a drain electrode 31D thereof, respectively. Further, a plurality of through-holes 36 obtained by removing a protective film so as to expose an embedded insulation layer of the SOI substrate are formed in a region where an intrinsic FET region 35 where the sensor FET is formed does not overlap with the MEMS region 34 and except for bridge regions 90, 90S, 90G, and 90H where lead-out wirings 20S, 20D, 20G, and 20H are formed and except for reinforced regions 91.
摘要翻译：实现了在低电压电源（例如，1.5至3V）下可以操作一年或更长时间的具有低功耗的MISFET型氢气传感器。传感器FET形成在MEMS区域34中，其中SOI衬底的Si衬底22被钻孔，并且加热器布线32被布置成折叠在Pi-Ti-O门28和源极电极31S之间传感器FET和Pt-Ti-O栅极28和漏电极31D之间。此外，在形成传感器FET的固有FET区域35的区域中形成有通过去除保护膜以暴露SOI衬底的嵌入绝缘层而获得的多个通孔36，其中MEMS本体不与MEMS 区域34，除了形成引出配线20S，20D，20G和20H的桥接区90,90S，90G和90H之外，除了加强区域91之外。

10. 发明授权

US5670804A PN-junction gate FET 失效
标题翻译： PN结栅极FET
公开(公告)号：US5670804A
公开(公告)日：1997-09-23
申请号：US501956
申请日：1995-07-13
申请人： Toshiyuki Usagawa , Akemi Sawada , Kenichi Tominaga
发明人： Toshiyuki Usagawa , Akemi Sawada , Kenichi Tominaga
IPC分类号： H01L29/417 , H01L29/80 , H01L27/088 , H01L31/0328
CPC分类号： H01L29/41758 , H01L29/802 , Y10S257/90
摘要： A semiconductor device is diclosed which has a PN-junction gate field effect transistor constituting a PN-junction gate with a semiconductor layer of opposite conductivity, an undoped semiconductor layer, and an active layer by depositing sources and drains made of semiconductor layers on the active layer of uniconductivity, depositing an undoped semiconductor layer whose band gap is greater than that of the active layer on the active layer between the opposing end surfaces of the sources and drains, and depositing a semiconductor layer of opposite conductivity on the undoped semiconductor layer away from the sources and drains. In particular, the present invention is effective for an enhancement type PN-junction power FET using compound semiconductors such as GaAs and capable of running with a single power supply and for a semi-conductor device integrating the enhancement type PN-junction power FET and a high-frequency low noise amplifier mono-lithically.
摘要翻译：一种半导体器件被封闭，其具有PN结栅极场效应晶体管，其构成具有相反导电性的半导体层的PN结栅极，未掺杂的半导体层和通过在半导体层上沉积源极和漏极的有源层沉积非掺杂半导体层的非掺杂半导体层，所述非掺杂半导体层的带隙大于源极和漏极的相对端面之间的有源层上的有源层的带隙，并且在未掺杂半导体层上沉积具有相反导电性的半导体层来源和渠道。特别地，本发明对于使用诸如GaAs的化合物半导体并且能够使用单个电源运行的增强型PN结功率FET以及集成增强型PN结功率FET的半导体器件和单频高频低噪声放大器。

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