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1. 发明授权

US5381027A Semiconductor device having a heterojunction and a two dimensional gas as an active layer 失效
标题翻译：具有异质结和二维气体作为有源层的半导体器件
公开(公告)号：US5381027A
公开(公告)日：1995-01-10
申请号：US134622
申请日：1993-10-12
申请人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
发明人： Toshiyuki Usagawa , Kenji Hiruma , Masahiko Kawata , Shigeo Goto , Katsuhiko Mitani , Masao Yamane , Susumu Takahashi , Tomonori Tanoue , Yoshinori Imamura
IPC分类号： H01L21/18 , H01L21/285 , H01L21/331 , H01L21/335 , H01L27/06 , H01L29/737 , H01L29/778 , H01L29/804 , H01L29/784
CPC分类号： H01L29/66318 , H01L21/182 , H01L21/28587 , H01L27/0605 , H01L29/66462 , H01L29/7373 , H01L29/7787
摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.
摘要翻译：本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。这些半导体器件可以降低源极栅极电阻和寄生基极电阻。本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

2. 发明申请

US20120217550A1 GAS SENSOR 有权
标题翻译：气体传感器
公开(公告)号：US20120217550A1
公开(公告)日：2012-08-30
申请号：US13508082
申请日：2010-10-01
申请人： Toshiyuki Usagawa
发明人： Toshiyuki Usagawa
IPC分类号： H01L27/088
CPC分类号： G01N27/4141 , G01N27/4148 , G01N33/005
摘要： A MISFET-type hydrogen gas sensor having low power consumption which can be operated for one year or longer at a low voltage power source (for example, 1.5 to 3 V) is achieved. A sensor FET is formed in a MEMS region 34 where a Si substrate 22 of a SOI substrate is bored, and a heater wiring 32 is arranged so as to be folded between a Pi-Ti—O gate 28 and a source electrode 31S of the sensor FET and between the Pt—Ti—O gate 28 and a drain electrode 31D thereof, respectively. Further, a plurality of through-holes 36 obtained by removing a protective film so as to expose an embedded insulation layer of the SOI substrate are formed in a region where an intrinsic FET region 35 where the sensor FET is formed does not overlap with the MEMS region 34 and except for bridge regions 90, 90S, 90G, and 90H where lead-out wirings 20S, 20D, 20G, and 20H are formed and except for reinforced regions 91.
摘要翻译：实现了在低电压电源（例如，1.5至3V）下可以操作一年或更长时间的具有低功耗的MISFET型氢气传感器。传感器FET形成在MEMS区域34中，其中SOI衬底的Si衬底22被钻孔，并且加热器布线32被布置成折叠在Pi-Ti-O门28和源极电极31S之间传感器FET和Pt-Ti-O栅极28和漏电极31D之间。此外，在形成传感器FET的固有FET区域35的区域中形成有通过去除保护膜以暴露SOI衬底的嵌入绝缘层而获得的多个通孔36，其中MEMS本体不与MEMS 区域34，除了形成引出配线20S，20D，20G和20H的桥接区90,90S，90G和90H之外，除了加强区域91之外。

3. 发明授权

US5670804A PN-junction gate FET 失效
标题翻译： PN结栅极FET
公开(公告)号：US5670804A
公开(公告)日：1997-09-23
申请号：US501956
申请日：1995-07-13
申请人： Toshiyuki Usagawa , Akemi Sawada , Kenichi Tominaga
发明人： Toshiyuki Usagawa , Akemi Sawada , Kenichi Tominaga
IPC分类号： H01L29/417 , H01L29/80 , H01L27/088 , H01L31/0328
CPC分类号： H01L29/41758 , H01L29/802 , Y10S257/90
摘要： A semiconductor device is diclosed which has a PN-junction gate field effect transistor constituting a PN-junction gate with a semiconductor layer of opposite conductivity, an undoped semiconductor layer, and an active layer by depositing sources and drains made of semiconductor layers on the active layer of uniconductivity, depositing an undoped semiconductor layer whose band gap is greater than that of the active layer on the active layer between the opposing end surfaces of the sources and drains, and depositing a semiconductor layer of opposite conductivity on the undoped semiconductor layer away from the sources and drains. In particular, the present invention is effective for an enhancement type PN-junction power FET using compound semiconductors such as GaAs and capable of running with a single power supply and for a semi-conductor device integrating the enhancement type PN-junction power FET and a high-frequency low noise amplifier mono-lithically.
摘要翻译：一种半导体器件被封闭，其具有PN结栅极场效应晶体管，其构成具有相反导电性的半导体层的PN结栅极，未掺杂的半导体层和通过在半导体层上沉积源极和漏极的有源层沉积非掺杂半导体层的非掺杂半导体层，所述非掺杂半导体层的带隙大于源极和漏极的相对端面之间的有源层上的有源层的带隙，并且在未掺杂半导体层上沉积具有相反导电性的半导体层来源和渠道。特别地，本发明对于使用诸如GaAs的化合物半导体并且能够使用单个电源运行的增强型PN结功率FET以及集成增强型PN结功率FET的半导体器件和单频高频低噪声放大器。

4. 发明授权

US09383329B2 Gas sensor and a method of manufacturing the same 有权
标题翻译：气体传感器及其制造方法
公开(公告)号：US09383329B2
公开(公告)日：2016-07-05
申请号：US13810516
申请日：2011-08-09
申请人： Toshiyuki Usagawa
发明人： Toshiyuki Usagawa
IPC分类号： G01N27/06 , B82Y15/00 , G01N27/414 , B82Y30/00
CPC分类号： G01N27/06 , B82Y15/00 , B82Y30/00 , G01N27/4141 , G01N27/4146
摘要： The gas sensor has a substrate, a gate insulating film arranged on the substrate, and a gate electrode arranged on the gate insulating film, wherein the gate electrode comprises a metal oxide mixture film produced by mixing an oxygen-doped amorphous metal that contains oxygen with crystals of an oxide of the metal and a platinum film formed on the metal oxide mixture film, the platinum film is composed of multiple platinum crystal grains and grain boundary regions that are present between the platinum crystal grains, the grain boundary regions are filled with a metal oxide mixture, and each of the platinum crystal grains is surrounded by the metal oxide mixture.
摘要翻译：气体传感器具有衬底，布置在衬底上的栅极绝缘膜和布置在栅极绝缘膜上的栅电极，其中栅电极包括通过将含有氧的掺杂氧的非晶态金属与金属氧化物的晶体和在金属氧化物混合物膜上形成的铂膜，铂膜由存在于铂晶粒之间的多个铂晶粒和晶界区域组成，晶界区域填充有金属氧化物混合物，并且每个铂晶粒被金属氧化物混合物包围。

5. 发明授权

US07541811B2 Apparatus for electron spin resonance CT 有权
标题翻译：电子自旋共振CT装置
公开(公告)号：US07541811B2
公开(公告)日：2009-06-02
申请号：US11774273
申请日：2007-07-06
申请人： Toshiyuki Usagawa
发明人： Toshiyuki Usagawa
IPC分类号： G01V3/00
CPC分类号： G01N24/10 , G01R33/3806 , G01R33/383
摘要： A compact, lightweight, and easy-to-use ESR-CT apparatus including a magnetic field leak line (5-G line) which is capable of imaging a small animal, such as a mouse, within 15 minutes, and of observing a desired region with a spatial resolution of 1 mm or less. A permanent magnet system is introduced of the apparatus includes pole pieces having a predetermined area which are opposed to each other through a measured space, yokes combined with the pole pieces, and a permanent magnet inserted in series so that at least one magnetic pole plane intersects perpendicularly to the closed magnetic circuit for magnetic coupling with the yokes. This makes it possible to locate a gradient coil system and a field scanning coil system sufficiently apart from end faces of the pole pieces, and to downsize the field scanning coil system so that the gradient field system is movable.
摘要翻译：一种紧凑，重量轻且易于使用的ESR-CT装置，其包括能够在15分钟内对小动物（例如鼠标）进行成像的磁场泄漏线（5-G线）和观察所需的空间分辨率为1mm以下的区域。引入永磁体系统，该装置包括具有通过测量空间彼此相对的预定区域的极片，与极片组合的轭铁和串联插入的永磁体，使得至少一个磁极平面与垂直于与磁轭耦合的封闭磁路。这使得可以将梯形线圈系统和场扫描线圈系统定位成与极片的端面充分分开，并且使场扫描线圈系统小型化，使得梯度场系统是可移动的。

6. 发明授权

US5567961A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5567961A
公开(公告)日：1996-10-22
申请号：US100718
申请日：1993-08-03
申请人： Toshiyuki Usagawa , Atsushi Takai , Hiroyuki Itoh
发明人： Toshiyuki Usagawa , Atsushi Takai , Hiroyuki Itoh
IPC分类号： H01L29/205 , H01L21/331 , H01L21/338 , H01L21/8222 , H01L21/8248 , H01L27/06 , H01L29/73 , H01L29/737 , H01L29/778 , H01L29/812 , H01L31/0328 , H01L31/0336 , H01L31/072
CPC分类号： H01L27/0623 , H01L27/0605 , H01L29/7373 , H01L29/7783
摘要： A semiconductor device may include a double hetero junction bipolar transistor and a field-effect transistor. The base of the bipolar transistor and the gate of the field-effect transistor are connected to each other to serve as an input terminal and the collector of the bipolar transistor and the drain of the field-effect transistor are connected to each other to serve as an output terminal. The bipolar transistor and the field-effect transistor may be created on a common substrate. In this case, both the bipolar and field-effect transistors can have the same multilayer/film structures.
摘要翻译：半导体器件可以包括双异质结双极晶体管和场效应晶体管。双极晶体管的基极和场效应晶体管的栅极彼此连接以用作输入端子，并且双极晶体管的集电极和场效应晶体管的漏极彼此连接以用作输出端子。双极晶体管和场效应晶体管可以在公共衬底上产生。在这种情况下，双极和场效晶体管都可以具有相同的多层/薄膜结构。

7. 发明授权

US5293084A High speed logic circuit 失效
标题翻译：高速逻辑电路
公开(公告)号：US5293084A
公开(公告)日：1994-03-08
申请号：US942181
申请日：1992-09-09
申请人： Hiroyuki Itoh , Toshiyuki Usagawa , Atsushi Takai
发明人： Hiroyuki Itoh , Toshiyuki Usagawa , Atsushi Takai
IPC分类号： H01L21/8249 , H01L27/06 , H01L29/737 , H03K17/567 , H03K19/094 , H03K19/08 , H01L29/161
CPC分类号： H03K19/09418 , H01L27/0605 , H01L29/7373 , H03K17/567
摘要： In a high speed logic circuit using a vertical hetero-junction bipolar transistor, in which two-dimensional carriers formed at a semiconductor hetero-junction interface are used as a base layer, the uppermost layer being a collector layer, the lowest layer being an emitter layer, two base electrodes making contact with the base layer are disposed so as to put a collector electrode, which is electrically in contact with the collector layer, therebetween. The base electrodes are used at the same time as a source electrode and a drain electrode, respectively, of a field effect transistor using the two-dimensional carriers as an active layer. The high speed logic circuit is so constructed that one of the base electrodes of the bipolar transistor is an input terminal; the other is connected with a power supply; the emitter is grounded; and the collector is an output terminal.
摘要翻译：在使用其中形成在半导体异质结界面处的二维载流子作为基底层的垂直异质结双极晶体管的高速逻辑电路中，最上层是集电极层，最低层是发射极配置与基底层接触的两个基底电极，以便在其间放置与集电体层电接触的集电极。基极分别与作为有源层的二维载流子的场效应晶体管的源电极和漏电极同时使用。高速逻辑电路被构造成使得双极晶体管的基极之一是输入端; 另一个与电源连接; 发射极接地; 收集器是输出端子。

8. 发明授权

US4805005A Semiconductor device and manufacturing method of the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US4805005A
公开(公告)日：1989-02-14
申请号：US783086
申请日：1985-10-02
申请人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
发明人： Toshiyuki Usagawa , Yasuhiro Shiraki , Yuichi Ono , Susumu Takahashi , Norikazu Hashimoto
IPC分类号： H01L21/338 , H01L21/8252 , H01L27/095 , H01L29/10 , H01L29/778 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7787 , H01L21/8252 , H01L29/1029 , H01L29/1075 , H01L29/8122
摘要： A semiconductor device and method of manufacturing the same. The device comprises a first n-type semiconductor layer and a second undoped semiconductor layer between which a hetero-junction is formed, and a third p-type embedded semiconductor layer, a gate metal formed without the exposure to air immediately after the third, second and first semiconductor layer are successively formed, and an external electrode connected with the third p-type embedded semiconductor layer, capable of controlling the carriers in the neighborhood of the hetero-junction. This semiconductor device greatly improves the controllability of the threshold voltage thereof, and provides the gate electrodes of good quality.
摘要翻译：一种半导体器件及其制造方法。该器件包括第一n型半导体层和在其之间形成异质结的第二未掺杂半导体层，以及第三p型嵌入式半导体层，在三分之一之后立即形成不暴露于空气的栅极金属，第二并且连续形成第一半导体层，以及与第三p型嵌入式半导体层连接的能够控制异质结附近的载流子的外部电极。该半导体器件极大地提高了其阈值电压的可控性，并且提供质量好的栅电极。

9. 发明授权

US09228973B2 Gas sensor 有权
标题翻译：气体传感器
公开(公告)号：US09228973B2
公开(公告)日：2016-01-05
申请号：US13508082
申请日：2010-10-01
申请人： Toshiyuki Usagawa
发明人： Toshiyuki Usagawa
IPC分类号： H01L27/088 , G01N27/414 , G01N33/00
CPC分类号： G01N27/4141 , G01N27/4148 , G01N33/005
摘要： A MISFET-type hydrogen gas sensor having low power consumption which can be operated for one year or longer at a low voltage power source (for example, 1.5 to 3 V) is achieved. A sensor FET is formed in a MEMS region 34 where a Si substrate 22 of a SOI substrate is bored, and a heater wiring 32 is arranged so as to be folded between a Pi-Ti—O gate 28 and a source electrode 31S of the sensor FET and between the Pt—Ti—O gate 28 and a drain electrode 31D thereof, respectively. Further, a plurality of through-holes 36 obtained by removing a protective film so as to expose an embedded insulation layer of the SOI substrate are formed in a region where an intrinsic FET region 35 where the sensor FET is formed does not overlap with the MEMS region 34 and except for bridge regions 90, 90S, 90G, and 90H where lead-out wirings 20S, 20D, 20G, and 20H are formed and except for reinforced regions 91.
摘要翻译：实现了在低电压电源（例如，1.5至3V）下可以操作一年或更长时间的具有低功耗的MISFET型氢气传感器。传感器FET形成在MEMS区域34中，其中SOI衬底的Si衬底22被钻孔，并且加热器布线32被布置成折叠在Pi-Ti-O门28和源极电极31S之间传感器FET和Pt-Ti-O栅极28和漏电极31D之间。此外，在形成传感器FET的固有FET区域35的区域中形成有通过去除保护膜以暴露SOI衬底的嵌入绝缘层而获得的多个通孔36，其中MEMS本体不与MEMS 区域34，除了形成引出配线20S，20D，20G和20H的桥接区90,90S，90G和90H之外，除了加强区域91之外。

10. 发明申请

US20130186178A1 GAS SENSOR AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：气体传感器及其制造方法
公开(公告)号：US20130186178A1
公开(公告)日：2013-07-25
申请号：US13810516
申请日：2011-08-09
申请人： Toshiyuki Usagawa
发明人： Toshiyuki Usagawa
IPC分类号： G01N27/06
CPC分类号： G01N27/06 , B82Y15/00 , B82Y30/00 , G01N27/4141 , G01N27/4146
摘要： The gas sensor has a substrate, a gate insulating film arranged on the substrate, and a gate electrode arranged on the gate insulating film, wherein the gate electrode comprises a metal oxide mixture film produced by mixing an oxygen-doped amorphous metal that contains oxygen with crystals of an oxide of the metal and a platinum film formed on the metal oxide mixture film, the platinum film is composed of multiple platinum crystal grains and grain boundary regions that are present between the platinum crystal grains, the grain boundary regions are filled with a metal oxide mixture, and each of the platinum crystal grains is surrounded by the metal oxide mixture.
摘要翻译：气体传感器具有衬底，布置在衬底上的栅极绝缘膜和布置在栅极绝缘膜上的栅电极，其中栅电极包括通过将含有氧的掺杂氧的非晶态金属与金属氧化物的晶体和在金属氧化物混合物膜上形成的铂膜，铂膜由存在于铂晶粒之间的多个铂晶粒和晶界区域组成，晶界区域填充有金属氧化物混合物，并且每个铂晶粒被金属氧化物混合物包围。

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